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SCN68562 PDF даташит

Спецификация SCN68562 изготовлена ​​​​«Philips» и имеет функцию, называемую «Dual universal serial communications controller DUSCC».

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Номер произв SCN68562
Описание Dual universal serial communications controller DUSCC
Производители Philips
логотип Philips логотип 

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SCN68562 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
SCN68562
Dual universal serial communications
controller (DUSCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips
Semiconductors









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SCN68562 Даташит, Описание, Даташиты
Philips Semiconductors
Dual universal serial communications controller (DUSCC)
Product specification
SCN68562
DESCRIPTION
The Philips Semiconductors SCN68562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN68562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently.
Each channel consists of a receiver, a transmitter, a 16-bit
multifunction counter/timer, a digital phase-locked loop (DPLL), a
parity/CRC generator and checker, and associated control circuits.
The two channels share a common bit rate generator (BRG),
operating directly from a crystal or an external clock, which provides
16 common bit rates simultaneously. The operating rate for the
receiver and transmitter of each channel can be independently
selected from the BRG, the DPLL, the counter/timer, or from an
external 1X or 16X clock, making the DUSCC well suited for
dual-speed channel applications. Data rates up to 4Mbits per
second are supported.
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs are provided. These inputs and outputs can be
optionally programmed for other functions.
FEATURES
General Features
Dual full-duplex synchronous/asynchronous receiver and
transmitter
Multiprotocol operation
BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
COP: BISYNC, DDCMP
ASYNC: 5–8 bits plus optional parity
Four character receiver and transmitter FIFOs
PIN CONFIGURATIONS
N PACKAGE
IACKN 1
A3 2
A2 3
A1 4
RTxDAKBN/ 5
GPI1BN
IRQN 6
RESETN 7
RTSBN/ 8
SYNOUTBN
TRxCB 9
RTxCB 10
DCDBN/ 11
SYNIBN
RxDB 12
TxDB 13
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
14
15
16
17
D7 18
D6 19
D5 20
D4 21
DTACKN 22
DTCN 23
GND 24
48 VDD
47 A4
46 A5
45 A6
44 RTxDAKAN/
GPI1AN
43 X1/CLK
42 X2/IDCN
41 RTSAN/
SYNOUTAN
40 TRxCA
39 RTxCA
DIP
38 DCDAN/
SYNIAN
37 Rxda
36 TxDA
35 TxDAKAN/
GPI2AN
34 RTxDRQAN/
GPO1AN
33 TxDRQAN/
GPO2AN/RTSAN
32 CTSAN/LCAN
31 D0
30 D1
29 D2
28 D3
27 DONEN
26 R/WN
25 CSN
INDEX
CORNER
8
A PACKAGE
7 1 47
46
PLCC
20
21
Pin Function
34
33
TOP VIEW
Pin Function
1 IACKN
2 A3
3 A2
4 A1
5 RTxDAKBN/
GPI1BN
6 IRQN
7 NC
8 RESETN
9 RTSBN/
SYNOUTBN
10 TRxCB
11 RTxCB
12 DCDBN/
SYNIBN
13 NC
14 RxDB
15 TxDB
16 TxDAKBN/
GPI2BN
17 RTxDRQBN/
GPO1BN
18 TxDRQBN/
GPO2BN/RTSBN
19 CTSBN/LCBN
20 D7
21 D6
22 D5
23 D4
24 DTACKN
25 DTCN
26 GND
27 CSN
28 R/WN
29 DONEN
30 D3
31 D2
32 D1
33 D0
34 NC
35 CTSAN/LCAN
36 TxDRQAN/
GPO2AN/RTSAN
37 RTxDRQAN/
GPO1AN
38 TxDAKAN/
GPI2AN
39 TxDA
40 RxDA
41 NC
42 DCDAN/
SYNIAN
43 RTxCA
44 TRxCA
45 RTSAN/
SYNOUTAN
46 X2/IDCN
47 X1/CLK
48 RTxDAKAN/
GPI1AN
49 A6
50 A5
51 A4
52 VDD
SD00222
Figure 1. Pin Configurations
1995 May 01
2 853-0831 15179









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SCN68562 Даташит, Описание, Даташиты
Philips Semiconductors
Dual universal serial communications controller (DUSCC)
Product specification
SCN68562
0 to 4MHz data rate
Programmable bit rate for each receiver and transmitter selectable
from:
16 fixed rates: 50 to 38.4k baud
One user-defined rate derived from programmable
counter/timer
External 1X or 16X clock
Digital phase-locked loop
Parity and FCS (frame check sequence LRC or CRC) generation
and checking
Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
Programmable data transfer mode: polled, interrupt, DMA, wait
DMA interface
Compatible with the Philips Semiconductors SCB68430 Direct
Memory Access Interface (DMAI) and other DMA controllers
Single- or dual-address dual transfers
Half- or full-duplex operation
Automatic frame termination on counter/timer terminal count or
DMA DONE
Interrupt capabilities
Daisy chain option
Vector output (fixed or modified by status)
Programmable internal priorities
Maskable interrupt conditions
Multi-function programmable 16-bit counter/timer
Bit rate generator
Event counter
Count received or transmitted characters
Delay generator
Automatic bit length measurement
Modem controls
RTS, CTS, DCD, and up to four general I/O pins per channel
CTS and DCD programmable autoenables for Tx and Rx
Programmable interrupt on change of CTS or DCD
On-chip oscillator for crystal
TTL compatible
Single +5V power supply
Asynchronous Mode Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
Up to two stop bits programmable in 1/16-bit increments
1X or 16X Rx and Tx clock factors
Parity, overrun, and framing error detection
False start bit detection
Start bit search 1/2-bit time after framing error detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmits up to 4Mbs and receive up to 2Mbps data rates
Character-Oriented Protocol Features
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line-fill on underrun
Idle in MARK or SYNs
Parity, FCS, overrun, and underrun error detection
BISYNC Features
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparent mode switching
Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for 1 field
Zero insertion and deletion
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
1995 May 01
3










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Номер в каталогеОписаниеПроизводители
SCN68562Dual universal serial communications controller DUSCCPhilips
Philips

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