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NJU8725 PDF даташит

Спецификация NJU8725 изготовлена ​​​​«New Japan Radio» и имеет функцию, называемую «CLASS D AMPLIFIER FOR DIGITAL AUDIO».

Детали детали

Номер произв NJU8725
Описание CLASS D AMPLIFIER FOR DIGITAL AUDIO
Производители New Japan Radio
логотип New Japan Radio логотип 

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NJU8725 Даташит, Описание, Даташиты
NJU8725
PRELIMINARY
CLASS D AMPLIFIER FOR DIGITAL AUDIO
! GENERAL DESCRIPTION
The NJU8725 is an 800mW-output class D
Amplifier featuring 6th ∆Σ modulation. It includes
Digital Attenuator, Mute, and De-emphasis circuits. It
converts Digital source input to PWM signal output
which is output PWM signal converted to analog
signal with simple external LC Filter. The NJU8725
realizes very high power-efficiency by class D
operation. Therefore, it is suitable for battery-powered
applications and others.
! PACKAGE OUTLINE
NJU8725V
! FEATURES
! PIN CONFIGURATION
# Stereo BTL Power Amplifier
# Sixth-order 32fS Over Sampling ∆Σ & PWM
# Internal 8fS Over Sampling Digital Filter
# Sampling Frequency : 96kHz (Max.)
# De-Emphasis
: 32kHz, 44.1kHz, 48kHz
# System Clock
: 256fS
# Digital Processing : Attenuator 107step, LOG Curve
VDD
STBY
TEST
MUTE
VDDL
: Mute
OUTLP
#
#
Digital Audio Interface : 16bit, 18bit
: I2S, LSB Justified, MSB Justified
Short Circuit Protection
VSSL
OUTLN
# Operating Voltage : 3.0 to 3.6V
VDDL
# Driving Voltage
: VDD to 5.25V
# C-MOS Technology
# Package Outline
: SSOP24
MODE
RST
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
F0/DATA
F1/REQ
F2/SCK
DIN
VDDR
OUTRP
VSSR
OUTRN
VDDR
LRCK
BCK
MCK
! BLOCK DIAGRAM
VDD
VSS
RST
MCK
LRCK
BCK
DIN
MUTE
STBY
MODE
F0/DATA
F1/REQ
F2/SCK
Power On
Reset Circuit
Synchronization
Circuit
Serial
Audio Data
Interface
System
Control
Short Circuit
Protection
8fS
Over Sampling
Digital Filter
32fS 6th ∆Σ
&
PWM
VDDL
OUTLP
VSSL
VDDL
OUTLN
VSSL
VDDR
OUTRP
VSSR
VDDR
OUTRN
VSSR
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NJU8725 Даташит, Описание, Даташиты
NJU8725
! TERMINAL DESCRIPTION
No.
SYMBOL
I/O
FUNCTION
1 VDD Logic Power Supply, VDD=3.3V
2
STBY
I
Standby Control Terminal
Low : Standby ON
High : Standby OFF
3
TEST
I
Manufacturer Testing Terminal
Normally connect to GND.
4
MUTE
I
Mute Control Terminal
Low : Mute ON
High : Mute OFF
5
VDDL
Lch Power Supply, VDDL=VDD to 5.0V
6
OUTLP
O Lch Positive Output Terminal
7
VSSL
Lch Power GND, VSSL=0V
8
OUTLN
O Lch Negative Output Terminal
9
VDDL
Lch Power Supply, VDDL=VDD to 5.0V
10
MODE
I
Control Mode selection Terminal
Low : Parallel Control Mode
High : Serial Control Mode
11
RST
I
Reset Terminal
Low : Reset ON
High : Reset OFF
12 VSS Logic Power GND, VSS=0V
13
MCK
I
Master Clock Input Terminal
256fS clock inputs this terminal.
14
BCK
I
Serial Audio Data Bit Clock Input Terminal
This clock must synchronize with MCK input signal.
15
LRCK
I
L/R Channel Clock Input Terminal
This clock must synchronize with MCK input signal.
16
VDDR
Rch Power Supply, VDDR=VDD to 5.0V
17
OUTRN
O Rch Negative Output Terminal
18
VSSR
Rch Power GND, VSSR=0V
19
OUTRP
O Rch Positive Output Terminal
20
VDDR
Rch Power Supply, VDDR=VDD to 5.0V
21 DIN I Serial Audio Data Input Terminal
MODE=”Low” : Serial Audio Interface Format Selection Terminal 2
22
F2/SCK
I
MODE=”High” : Control Register Data Shift Clock Input Terminal
The data is fetched into the control register by rise edge of SCK
signal.
23
F1/REQ
I
MODE=”Low” : Serial Audio Interface Format Selection Terminal 1
MODE=”High” : Control Register Data Request Input Terminal
24
F0/DATA
I
MODE=”Low” : Serial Audio Interface Format Selection Terminal 0
MODE=”High” : Control Register Data Input Terminal
! INPUT TERMINAL STRUCTURE
VDD
Input Terminal
VSS
Inside Circuit
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NJU8725 Даташит, Описание, Даташиты
NJU8725
! FUNCTIONAL DESCRIPTION
(1) Signal Output
PWM signals of L channel and R output from OUTLP/LN and OUTRP/RN terminals respectively. These signals
are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from
VDDL, VDDR, VSSL, and VSSR are required high response power supply against voltage fluctuation like as switching
regulator because Output THD is effected by power supply stability.
(2) Master Clock
Master Clock is 256fS clock into MCK terminal for the internal circuit operation clock.
(3) Reset
“L” level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This
initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset
signal. This Reset signal initializes the internal function setting registers also. During initialization, the
output-drivers output GND level. The reset equivalent circuit is shown bellow.
RST
Power on Reset
CLK
(About 10kHz)
DDDDDDDD
Figure 1. Reset Equivalent Circuit
Internal Reset
(4) 8fS Over Sampling Digital Filter
8fS Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise.
It realizes Attenuation and De-Emphasis function by serial function control.
(5) 32fS 6th ∆Σ & PWM
32fS 6th ∆Σ & PWM convert from Audio data of the 8fS Over Sampling Digital Filter to the 32fS one bit PWM
data.
(6) Short Circuit Protection
Short Circuit Protection protects IC with output terminal of high-impedance condition when output terminal is
shorted to GND or other output terminal.
The high-impedance condition is released automatically with master clock input, not released without master
clock input.
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