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PDF SED1351 Data sheet ( Hoja de datos )
| Número de pieza | SED1351 | |
| Descripción | Graphics LCD Controller | |
| Fabricantes | Seiko | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SED1351 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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SED1351
SED1351
GRAPHICS LCD CONTROLLER
s DESCRIPTION
The SED1351F is a graphics LCD controller capable of controlling medium to large resolution displays. It
transfers data from MPU to external frame buffer RAM and converts this data to display signals for LCD
drivers. The SED1351F can display images with 4 gray shades and support display duty cycle as high as 1/
1024.
The SED1351F is designed to achieve high efficiency and data throughput to the LCD. It has a cycle steal
mode which allows MPU to access frame buffer RAM without interfering with the display operation. The
SED1351F can directly interface with up to eight 64K-bit SRAMs or two 256K-bit SRAMs.
The SED1351F can operate with either 5V or 3V power supply. The 5V version chip is the SED1351F0A and
the 3V version chip is the SED1351FLB.
s FEATURES
• Low-power CMOS technology
• 8-bit or 16-bit MPU data interface
• Direct interface with 80xx, Z80 and 68xxx MPU
• 4- or 8-bit panel data bus for single panel and
4-bit bus for dual panel
• Support logical OR of layers and panel division
• Smooth vertical scrolling
• Virtual screen display up to 1024
• Binary mode (on/off only) generates black &
white images
• Gray mode (on/off and two gray steps) gener-
ates images with 4 gray shades
s SYSTEM BLOCK DIAGRAM
• Maximum number of rows
Binary mode ............ 2048
Gray mode .............. 1024
• Maximum number of rows:
Single panel ............ 1024
Dual panel ............... 2048
• Maximum display sizes when 64K-byte SRAMs
are used:
Binary mode ............ 2048 × 256 / 1024 × 512
Gray mode .............. 1024 × 256 / 512 × 512
• Available models:
SED1351F0A ............ 5V, QFP5-100 pin
SED1351FLB ............ 3V,QFP15-100 pin
CLOCK
MPU
80xx
Z80
68xxx
DATA
CONTROL
ADDRESS
SED1351F
SRAM
8 of 8K × 8 or
2 of 32K × 8
MONO LCD
197
1 page  
s SUPPORTED RESOLUTIONS
Display
RAM
8K
16K
Maximum Display Size
Monochrome
4 Grayscale
X YX Y
256 × 256 256 × 128
512 × 256 256 × 256
24K 512 × 384 384 × 256
32K 512 × 512 512 × 256
48K 768 × 512 512 × 384
56K 896 × 512 512 × 448
64K 1024 × 512 512 × 512
SRAM
Type
1 of 8K × 8
2 of 8K × 8
3 of 8K × 8
4 of 8K × 8
1 of 32K × 8
6 of 8K × 8
7 of 8K × 8
8 of 8K × 8
2 of 32K × 8
CPU
Interface
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
16 bit
SED1351
SRAM
Interface
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
8 bit
16 bit
8 bit
16 bit
s BLOCK DIAGRAM
IOCS,LOWR, IORD
MEMCS, MEMWR, MEMRD
AB0 ~ AB15
BHE
DB0 ~ DB15
READY
RESET
MPUSEL, MPUCLK
I/O Control
Address Buffer
Data Buffer
Basic Training
Generation
Oscillator
Control Register
R1 to
R15
16 Bits
Refresh
Address
Counter
VRAM
Control
MPX
Display Timing
Control
Display Data
Control
MPX
LCDENB
XSCL
LP
YD
WF
UD0 ~ UD3
LD0 ~ LD3
OSC1
OSC2
VA0 ~ VA15
VCS0 ~ VCS4
VWE
VD0 ~ VD15
201
5 Page 
SED1351
s PIN DESCRIPTION
1. System Connector Terminals (at MPU)
Pin Name
DB0 to DB15
AB0 to AB15
BHE
IOCS
IOWR
IORD
MEMCS
MEMWR
MEMRD
READY
MPUCLK
MPUSEL
RESET
Type
I/O
I
I
I
I
I
I
I
I
O
I
I
I
F0A
Pin No.
30 to 45
14 to 29
13
3
4
5
6
7
8
9
10
12
11
FLB
Pin No.
28 to 43
12 to 27
11
1
2
3
4
5
6
7
8
10
9
Drv Description
These pins are interfaced with the MPU data bus.
When using an 8-bit MPU, connect DB8 to DB15 to
VDD.
These pins are interfaced with the MPU address bus.
If multiplexed address signals are used, connect them
via latch circuits. A control register is selected by AB0
to AB3. Correspondence of the MPU address bus to
the VRAM address bus is such that ABi = VAi (where
i is a pin number).
This signal is a bus high enable signal where a 16-bit
MPU is used. It goes “L” (low) when an odd address is
encountered. When using an 8-bit MPU configuration,
connect the BHE pin to VDD.
This pin selects a control register contained in the
SED1351. It is “L” active, and must be assigned to
MPU I/O space.
This signal is used for writing data into a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an OUT instruction
from the MPU.
This signal is used for reading data from a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an IN instruction from
the MPU.
This signal is used for selecting VRAM. It is “L” active,
and must be assigned to MPU memory space.
This signal is used for writing data to the VRAM. It is “L”
active, and must go “L” when it encounters a memory
write instruction from the MPU.
This signal is used for reading data from the VRAM. It
is “L” active, and must go “L” when it encounters a
memory read instruction from the MPU.
This signal requests the MPU to wait. It goes “L” by the
falling edge of IOCS or MEMCS. It goes “H” by the
rising edge of MPUCLK after completion of the
SED1351 internal processing. Since READY is not a
tri-state pin, it needed not be pulled up and must be
connected directly to the READY (WAIT) terminal of
the MPU.
This pin accepts an MPU clock. The MPU wait state is
cleared by the rising edge of MPUCLK.
This signal is connected to either VDD or VSS for
selection of an MPU.
MPUSEL = VSS 8-bit MPU (e.g., Z80, V20, i8088)
MPUSEL = VDD 16-bit MPU (e.g., V30, i8086)
The MPU reset signal comes to this pin. It is “H” active,
and initializes a control register.
207
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SED1351.PDF ] | |
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