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PDF S5L9291X Data sheet ( Hoja de datos )
| Número de pieza | S5L9291X | |
| Descripción | signal processing LSI for the CD | |
| Fabricantes | SAMSUNG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S5L9291X (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DIGITAL SIGNAL PROCESSOR
S5L9291X
INTRODUCTION
S5L9291X is a signal processing LSI for the CD. Digital processing
functions (EFM demodulation, error correction), spindle motor servo
processing, compression for anti-rolling and anti-shock, expandable
memory control functions (4M, 16M, 64M EDO/Fast Page DRAM and
16M, 32M, 64M, 128M, 256M SDRAM ), 10-band EQ (Equalizer) Filter,
CD-Text and 1-bit DAC for the CD-MP3 Interface are installed in
S5L9291X.
FEATURES
100-TQFP-1414
• Signal processing part
EFM data demodulation
Frame sync detection, protection, insertion
Sub code data processing (Q data CRC check, Q data register installed)
Error correction (C1: 2 error correction, C2: 4 erasure correction)
Installed 16K SRAM for De-interleave
Interpolation
Digital audio interface
CLV/pseudo-CAV servo control
Wide capture range digital PLL ( ± 50%)
CD-Text
Variable speed CLV Control (×1 to ×2 )
CD MP3 Interface
• Digital filter, DAC part
4 times over sampling digital filter
Digital de-emphasis
10 Band EQ function
Sigma-delta stereo DAC installed
Audio L.P.F installed
• Memory control part
4/5/6 bit compression and expandable control
Full bit control
4M/16M/64M, ×4, ×8, ×16 EDO/FastPage DRAM Support
16M/64M/128M/256M, 32M(16M 2EA), ×8, ×16 SDRAM Support
ORDERING INFORMATION
Device
S5L9291X01-T0R0
Package
100-TQFP-1414
Supply Voltage
2.7 to 3.3V
Operating Temperature
-20 to +75°C
1
1 page  
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION (Continued)
Pin No
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Symbol
SBCK
SBDT
MUTE
C4M
TEST1
TEST2
LCHOUT
VDDA_DAC
VHALF
VREF
VSSA_DAC
RCHOUT
VDDD_DAC
VSSD_DAC
TEST3
DATX
JITB
C2PO
RFCK
MNT0
MNT1
MNT2
MNT3
MNT4
MNT5
VSSD3
VDDD4
D15
D14
D13
D12
D11
D10
D9
I/O Description
I Subcode data transferring bit clock
I/O Subcode data serial output
I System mute at "H"
O 4.2336MHz clock output
I Test Input
I Test Input
O Left-Channel audio output through DAC
- Analog Power for DAC
O Reference Voltage output for bypass
O Reference Voltage output for bypass
- Analog Ground for DAC
O Right-Channel audio output through DAC
- Digital Power for DAC
- Digital Ground for DAC
I Test Input
O Digital audio data output
I/O Internal SRAM jitter margin status output
O C2 pointer Output
I/O Read base clock output
I/O Monitoring signal output
I/O Monitoring signal output
I/O Monitoring signal output
I/O Monitoring signal output
I/O Monitoring signal output
I/O Monitoring signal output
- Digital Ground
- Digital Power
I/O DRAM data Input/Output 15 (3-State Output)
I/O DRAM data input/output 14 (3-State Output)
I/O DRAM data input/output 13 (3-State Output)
I/O DRAM data input/output 12 (3-State Output)
I/O DRAM data input/output 11 (3-State Output)
I/O DRAM data input/output 10 (3-State Output)
I/O DRAM data input/output 9 (3-State Output)
S5L9291X
5
5 Page 
DIGITAL SIGNAL PROCESSOR
S5L9291X
EDO-DRAM, FAST-PAGE DRAM INTERFACE TIMING
Read Cycle
RAS
CAS
ADDR
2T
1T 1T
ROW ADDRESS
1T = 59ns/2 at Bus X4
1T = 59ns at Bus X8, X16
4T 2T
2T
4T
COLUMN ADDRESS
WE
DATA[3:0]
1T 1T
DATA-OUT
Don't Care
OE = GND
Write Cycle
RAS
CAS
ADDR
1T = 59ns/2 at Bus X4
1T = 59ns at Bus X8, X16
4T 2T
2T 2T
1T 1T
ROW ADDRESS
4T
COLUMN ADDRESS
WE
DATA[3:0]
2T 2T
DATA-IN
Don't Care
OE = GND
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S5L9291X.PDF ] | |
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