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PDF HD6413002 Data sheet ( Hoja de datos )
| Número de pieza | HD6413002 | |
| Descripción | HD6413002 | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD6413002 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
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Renesas Technology Corp. DataShee
Customer Support Dept.
April 1, 2003
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Contents
Section 1 Overview ..................................................................................................... 1
1.1 Overview ........................................................................................................................ 1
1.2 Block Diagram................................................................................................................ 5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Functions .................................................................................................. 8
1.4 Pin Functions .................................................................................................................. 12
Section 2 CPU ............................................................................................................... 17
2.1 Overview ........................................................................................................................ 17
2.1.1 Features........................................................................................................... 17
2.1.2 Differences from H8/300 CPU ....................................................................... 18
2.2 CPU Operating Modes.................................................................................................... 19
2.3 Address Space................................................................................................................. 20
2.4 Register Configuration.................................................................................................... 21
2.4.1 Overview......................................................................................................... 21
2.4.2 General Registers............................................................................................ 22
2.4.3 Control Registers ............................................................................................ 23
2.4.4 Initial CPU Register VDaalutaesS..h..e..e..t.4...U.....c..o..m........................................................ 24
2.5 Data Formats................................................................................................................... 25
2.5.1 General Register Data Formats....................................................................... 25
2.5.2 Memory Data Formats.................................................................................... 26
2.6 Instruction Set................................................................................................................. 28
2.6.1 Instruction Set Overview ................................................................................ 28
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2.6.2
2.6.3
Instructions and Addressing Modes................................................................
Tables of Instructions Classified by Function ................................................
23D90 ataShee
2.6.4 Basic Instruction Formats ............................................................................... 40
2.6.5 Notes on Use of Bit Manipulation Instructions .............................................. 41
2.7 Addressing Modes and Effective Address Calculation .................................................. 41
2.7.1 Addressing Modes .......................................................................................... 41
2.7.2 Effective Address Calculation ........................................................................ 44
2.8 Processing States ............................................................................................................ 48
2.8.1 Overview......................................................................................................... 48
2.8.2 Program Execution State ................................................................................ 49
2.8.3 Exception-Handling State............................................................................... 49
2.8.4 Exception-Handling Sequences ...................................................................... 51
2.8.5 Bus-Released State ......................................................................................... 52
DataSheet4U2.c.8o.m6 Reset State ...................................................................................................... 52
2.8.7 Power-Down State .......................................................................................... 52
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10.4 Operation ........................................................................................................................ 317
10.4.1 Overview......................................................................................................... 317
10.4.2 Basic Functions............................................................................................... 318
10.4.3 Synchronization .............................................................................................. 328
10.4.4 PWM Mode .................................................................................................... 330
10.4.5 Reset-Synchronized PWM Mode ................................................................... 334
10.4.6 Complementary PWM Mode.......................................................................... 337
10.4.7 Phase Counting Mode..................................................................................... 347
10.4.8 Buffering......................................................................................................... 349
10.4.9 ITU Output Timing......................................................................................... 356
10.5 Interrupts ........................................................................................................................ 358
10.5.1 Setting of Status Flags .................................................................................... 358
10.5.2 Clearing of Status Flags.................................................................................. 360
10.5.3 Interrupt Sources and DMA Controller Activation ........................................ 361
10.6 Usage Notes .................................................................................................................... 362
Section 11 Programmable Timing Pattern Controller ......................................... 377
11.1 Overview ........................................................................................................................ 377
11.1.1 Features........................................................................................................... 377
11.1.2 Block Diagram................................................................................................ 378
11.1.3 TPC Pins ......................................................................................................... 379
11.1.4 Registers ...................D...a..t..a..S...h..e..e..t.4...U.....c..o..m........................................................ 380
11.2 Register Descriptions...................................................................................................... 381
11.2.1 Port A Data Direction Register (PADDR) ...................................................... 381
11.2.2 Port A Data Register (PADR) ......................................................................... 381
11.2.3 Port B Data Direction Register (PBDDR) ...................................................... 382
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11.2.4 Port B Data Register (PBDR) ......................................................................... 382
11.2.5 Next Data Register A (NDRA)....................................................................... 38D3 ataShee
11.2.6 Next Data Register B (NDRB) ....................................................................... 385
11.2.7 Next Data Enable Register A (NDERA) ........................................................ 387
11.2.8 Next Data Enable Register B (NDERB)......................................................... 388
11.2.9 TPC Output Control Register (TPCR)............................................................ 389
11.2.10 TPC Output Mode Register (TPMR).............................................................. 392
11.3 Operation ........................................................................................................................ 394
11.3.1 Overview......................................................................................................... 394
11.3.2 Output Timing................................................................................................. 395
11.3.3 Normal TPC Output........................................................................................ 396
11.3.4 Non-Overlapping TPC Output........................................................................ 398
11.3.5 TPC Output Triggering by Input Capture....................................................... 400
DataSh1e1.e4t4UU.csoamge Notes .................................................................................................................... 401
11.4.1 Operation of TPC Output Pins........................................................................ 401
11.4.2 Note on Non-Overlapping Output .................................................................. 401
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6413002.PDF ] | |
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