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CH7013A PDF даташит

Спецификация CH7013A изготовлена ​​​​«Chrontel» и имеет функцию, называемую «Digital PC to TV Encoder».

Детали детали

Номер произв CH7013A
Описание Digital PC to TV Encoder
Производители Chrontel
логотип Chrontel логотип 

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CH7013A Даташит, Описание, Даташиты
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Digital PC to TV Encoder
CH7013A
1. FEATURES
• Pin and function compatible with CH7003
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15, 16 or 24-bit) video data in both
non-interlaced and interlaced formats
• True scale rendering engine supports undescan
operations for various graphics resolutions¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through serial port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin TQFP (1.4 mm)
2. GENERAL DESCRIPTION
Chrontel’s CH7013A digital PC to TV encoder is a stand-
alone integrated circuit providing a robust solution for TV
output. It provides a universal digital input port to accept a
pixel data stream from a compatible VGA controller (or
equivalent) and converts this directly into NTSC or PAL TV
format.
This circuit integrates a digital NTSC/PAL encoder with 9-
bit DAC interface, and new adaptive flicker filter, and high
accuracy low-jitter phase locked loop to create outstanding
quality video. Through its true scale scaling and de-
flickering engine, the CH7013A supports full vertical and
horizontal underscan capability and operates in 5 different
resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7013A ideal for system-level
PC solutions. All features are software programmable
through a serial port, to enable a complete PC solution using
a TV as the primary display.
Patent number 5,781,241
¥ Patent number 5,914,753
LINE
MEMORY
YUV-RGB CONVERTER
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING & DEFLICKERING
ENGINE
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
SERIAL CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC GENERATOR
Y/R
C/G
CVBS/B
RSET
CLOCK DATA
ADDR
XCLK
H V XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
201-0000-041 Rev. 1.5, 9/1/2004
1









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CH7013A Даташит, Описание, Даташиты
CHRONTEL
3. PIN DESCRIPTIONS
3.1 Package Diagram
CH7013A
D[3]
D[4]
D[5]
D[6]
DVDD
D[7]
D[8]
DGND]
D[9]
D[10]
D[11]
1
2
3
4
5
6
7
8
9
10
11
CHRONTEL
CH7013A
33 XO/FIN
32 XI
31 AVDD
30 DVDD
29 ADDR
28 DGND
27 SCCLOCK
26 SDDATA
25 VDD
24 RSET
23 GND
Figure 2: 44-PIN TQFP (1.4 mm)
2 201-0000-041 Rev. 1.5, 9/1/2004









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CH7013A Даташит, Описание, Даташиты
CHRONTEL
CH7013A
3.2 Pin Descriptions
Table 1. Pin Descriptions
44Pin
TQFP
Type Symbol
15,14,
13,12,
11,10,
9,7,6,
4,3,
2,1,
44,43,42
In
D15-D0
37 Out P-OUT
39 In XCLK
41 In/Out
V
40 In/Out
H
35 Out BCO
32 In
XI
33 In XO/FIN
24 In RSET
22 Out Y/R
21 Out C/G
Description
Digital Pixel Inputs
These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed
or 16-bit non-multiplexed formats, determined by the input mode setting (see
Registers and Programming section). Inputs D0 - D7 are used when operating in 8-
bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode.
Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and
timing sequence for each mode is described in the section on Digital Input Port.
Pixel Clock Output
The CH7013A, operating in master mode, provides a pixel data clocking signal to
the VGA controller. This pin provides the pixel clock output signal (adjustable as X,
2X or 3X) to the VGA controller (see the section on Digital Video Interface and
Registers and Programming for more details). The capacitive loading on this pin
should be kept to a minimum.
Pixel Clock Input
To operate in a pure master mode, the P-OUT signal should be connected to the
XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a
reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-
OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7013A
accepts an external pixel clock input at this pin. The capacitive loading on this pin
should be kept to a minimum.
Vertical Sync Input/Output
This pin accepts the vertical sync signal from the VGA controller, or outputs a
vertical sync to the VGA controller. The capacitive loading on this pin should kept to
a minimum.
Horizontal Sync Input/Output
This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal
sync to the VGA controller. The capacitive loading on this pin should be kept to a
minimum.
Buffered Clock Output
This pin provides a buffered output of the 14.31818 MHz crystal input frequency for
other devices and remains active at all times (including power-down). The output
can also be selected to be other frequencies (see Registers and Programming).
Crystal Input
A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be attached between
XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI
should be connected to ground.
Crystal Output or External Fref
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An
external CMOS compatible clock can be connected to XO/FIN as an alternative.
Reference Resistor
A 360 resistor with short and wide traces should be attached between RSET and
ground. No other connections should be made to this pin.
Luminance Output
A 75 termination resistor with short traces should be attached between Y and
ground for optimum performance. In normal operating modes other than SCART,
this pin outputs the luma video signal. In SCART mode, this pin outputs the red
signal.
Chrominance Output
A 75 termination resistor with short traces should be attached between C and
ground for optimum performance. In normal operating modes other than SCART,
this pin outputs the chroma video signal. In SCART mode, this pin outputs the
green signal.
201-0000-041 Rev. 1.5, 9/1/2004
3










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