PDF HM5118165 Data sheet ( Hoja de datos )

Número de pieza	HM5118165
Descripción	16M EDO DRAM
Fabricantes	Hitachi
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No Preview Available ! HM5118165 Series 16 M EDO DRAM (1-Mword × 16-bit) 1 k Refresh ADE-203-636D (Z) Rev. 4.0 Nov. 1997 Description The Hitachi HM5118165 is a CMOS dynamic RAM organized as 1,048,576-word × 16-bit. It employs the most advanced 0.5 µm CMOS technology for high performance and low power. The HM5118165 offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in 42-pin plastic SOJ and 50-pin plastic TSOP II. Features • Single 5 V (±10%) • Access time : 50 ns/60 ns/70 ns (max) • Power dissipation  Active mode : 1045 mW/935 mW/825 mW (max)  Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Refresh cycles  1024 refresh cycles : 16 ms : 128 ms (L-version) • 4 variations of refresh  RAS-only refresh  CAS-before-RAS refresh  Hidden refresh  Self refresh (L-version) • 2CAS-byte control • Battery backup operation (L-version) 1 page HM5118165 Series Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open Standby L L H H L Valid Lower byte Read cycle L HL H L Valid Upper byte L L L H L Valid Word L L H L2 D Open Lower byte Early write cycle L HL L2 D Open Upper byte L L L L2 D Open Word L L H L2 H Undefined Lower byte Delayed write cycle L H L L2 H Undefined Upper byte L L L L2 H Undefined Word L L H H to L L to H Valid Lower byte Read-modify-write cycle L HL H to L L to H Valid Upper byte L L L H to L L to H Valid Word L HH D D Open Word RAS-only refresh cycle H to L H L D D Open Word CAS-before-RAS refresh cycle or H to L L H D D Open Word Self refresh cycle (L-version) H to L L L D D Open Word L L L H H Open Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. tWCS ≥ 0 ns Early write cycle tWCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. 5 5 Page HM5118165 Series EDO Page Mode Cycle HM5118165 -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit EDO page mode cycle time t HPC EDO page mode RAS pulse width tRASP Access time from CAS precharge tCPA RAS hold time from CAS precharge tCPRH Output data hold time from CAS low tDOH CAS hold time referred OE t COL CAS to OE setup time t COP Read command hold time from CAS precharge t RCHC 20 — 25 — 30 — ns — 100000 — 100000 — 100000 ns — 28 — 35 — 40 ns 28 — 35 — 40 — ns 3— 3— 3— ns 7— 10 — 13 — ns 5— 5— 5— ns 28 — 35 — 40 — ns Notes 25 16 9, 17, 22 9 EDO Page Mode Read-Modify-Write Cycle HM5118165 -5 -6 Parameter Symbol Min Max Min EDO page mode read-modify-write tHPRWC 57 — 68 cycle time WE delay time from CAS precharge tCPW 45 — 54 -7 Max Min — 79 — 62 Max Unit — ns — ns Notes 14, 22 Refresh Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 16 128 Unit Note ms 1024 cycles ms 1024 cycles 11 11 Page

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