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CAT24FC02 PDF даташит

Спецификация CAT24FC02 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each».

Детали детали

Номер произв CAT24FC02
Описание 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT24FC02 Даташит, Описание, Даташиты
CAT24FC02
2-kb I2C Serial EEPROM
FEATURES
I 400 kHz (2.5 V) I2C bus compatible
I 2.5 to 5.5 volt operation
I Low power CMOS technology
I 16-byte page write buffer
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, SOIC, TSSOP and MSOP packages
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
DESCRIPTION
The CAT24FC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC02 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, SOIC, TSSOP and MSOP
packages.
PIN CONFIGURATION
DIP Package (P, L, GL) SOIC Package (J, W, GW)
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8
7
6
5
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
MSOP Package (R, Z, GZ)
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 2.5 V to 5.5 V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SDA
START/STOP
LOGIC
XDEC
E2PROM
WP CONTROL
LOGIC
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1045, Rev. G









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CAT24FC02 Даташит, Описание, Даташиты
CAT24FC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ............ 2.0 V to VCC + 2.0 V
VCC with Respect to Ground ............. 2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
NEND
Endurance
TDR Data Retention
VZAP
ILTH(4)
ESD Susceptibility
Latch-up
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
*COMMENT
Stresses above those listed under Absolute Maximum Ratingsmay
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Min
1,000,000
100
4000
100
Typ
Max Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
ICC
Power Supply Current (Read)
fSCL = 400 kHz
1 mA
ICC
ISB(5)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
fSCL = 400 kHz
VIN = GND or VCC
3 mA
1 µA
ILI
Input Leakage Current
VIN = GND to VCC
1 µA
ILO
Output Leakage Current
VOUT = GND to VCC
1 µA
VIL Input Low Voltage
1
VCC x 0.3
V
VIH Input High Voltage
VCC x 0.7
VCC + 1.0 V
VOL Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
0.4 V
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
VI/O = 0 V
CIN(3)
Input Capacitance (other pins)
VIN = 0 V
Min Typ
Max Units
8 pF
6 pF
Note:
(1) The minimum DC input voltage is 0.5 V. During transitions, inputs may undershoot to 2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1.0 V to VCC + 1.0 V.
(5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range.
Doc. No. 1072, Rev. G
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice









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CAT24FC02 Даташит, Описание, Даташиты
CAT24FC02
A.C. CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
2.5 V - 5.5 V
Min Max
0 400
100
900
1300
600
1300
600
600
0
100
300
300
600
100
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Power-Up Timing(1)(2)
Symbol
Parameter
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Min Typ
Max
1
1
Units
ms
ms
Write Cycle Limits
Symbol
Parameter
tWR Write Cycle Time
Min Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1072, Rev. G










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