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CA3304 PDF даташит

Спецификация CA3304 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «4-Bit / 25 MSPS / Flash A/D Converters».

Детали детали

Номер произв CA3304
Описание 4-Bit / 25 MSPS / Flash A/D Converters
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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CA3304 Даташит, Описание, Даташиты
CA3304, CA3304A
August 1997
4-Bit, 25 MSPS,
Flash A/D Converters
Features
• CMOS/SOS Low Power with Video Speed (Typ) . . 25mW
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 25MHz Sampling Rate (40ns Conversion Time) at 5V
Supply
• 4-Bit Latched Three-State Output with Overflow and
Data Change Outputs
1/8 LSB Maximum Nonlinearity (A Version)
• Inherent Resistance to Latch-Up Due to SOS Process
• Bipolar Input Range with Optional Second Supply
• Wide Input Bandwidth (Typ) . . . . . . . . . . . . . . . . 25MHz
Applications
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
• RSSI Circuits
Description
The Intersil CA3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
The CA3304 operates over a wide, full-scale signal input
voltage range of 0.5V up to the supply voltage. Power
consumption is as low as 10mW, depending upon the clock
frequency selected.
The intrinsic high conversion rate makes the CA3304 types
ideally suited for digitizing high speed signals. The overflow
bit makes possible the connection of two or more CA3304s
in series to increase the resolution of the conversion system.
A series connection of two CA3304s may be used to pro-
duce a 5-bit, 25MHz converter. Operation of two CA3304s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 25MHz to 50MHz). A data change pin
indicates when the present output differs from the previous,
thus allowing compaction of data storage.
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the CA3304. Fifteen com-
parators are required to quantize all input voltage levels in this
4-bit converter, and the additional comparator is required for
the overflow bit.
Ordering Information
PART NUMBER LINEARITY (INL, DNL)
CA3304E
±0.25 LSB
CA3304AE
±0.125 LSB
CA3304M
±0.25 LSB
CA3304AM
±0.125 LSB
CA3304D
±0.25 LSB
CA3304AD
±0.125 LSB
Pinout
SAMPLING RATE
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
25MHZ (40ns)
25MHz (40ns)
25MHz (40ns)
TEMP. RANGE (oC)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC (W)
16 Ld SOIC (W)
16 Ld SBDIP
16 Ld SBDIP
CA3304 (SBDIP, PDIP, SOIC)
TOP VIEW
PKG. NO.
E16.3
E16.3
M16.3
M16.3
D16.3
D16.3
BIT 1 (LSB) 1
BIT 2 2
BIT 3 3
BIT 4 4
DATA CHANGE (DC) 5
OVERFLOW (OF) 6
CE2 7
VSS 8
16 VDD
15 CLK
14 VAA-
13 VREF-
12 VREF+
11 VIN
10 VAA+
9 CE1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-7
File Number 1790.2









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CA3304 Даташит, Описание, Даташиты
CA3304, CA3304A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range (VDD or VAA+)
(Voltage Referenced to VSS or VAA- Terminal,
Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V
Input Voltage Range
CE1, CE2 Inputs . . . . . . . . . . . . . . . . . . . VSS -0.5V to VDD +0.5V
Clock, VREF+, VREF-, VIN Inputs . . . . . VAA- -0.5V to VAA- +0.5V
DC Input Current, Any Input . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Operating Conditions
Recommended Supply Voltage Range (VDD or VAA+) . . . . .3V to 7.5V
Recommended VAA+ Voltage Range . . . . . . VDD -1V to VDD +2.5V
Recommended VAA- Voltage Range . . . . . . . VSS -2.5V to VSS +1V
Operating Temperature
CA3304D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CA3304E, CA3304M. . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . . . .
80
22
PDIP Package . . . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . . . . 100
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum
Maximum
Storage Temperature Range (TSTG)
Lead Temperature (Soldering 10s) . .
.
.
.
.
.
.
-65oC
......
to
..
150oC
300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF- = VSS = GND, fCLK = 25MHz
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
SYSTEM PERFORMANCE
Resolution
Input Errors
Integral Linearity
Error
CA3304A
CA3304
Differential Linearity
Error
CA3304A
CA3304
Offset Error
(Unadjusted)
CA3304A
CA3304
Gain Error
(Unadjusted)
CA3304A
CA3304
DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale)
Conversion Timing Aperture Delay
Signal to Noise Ratio, SNR
RMS Signal
=
RMS Noise
fS = 25MHz, fIN = 100kHz
fS = 25MHz, fIN = 5MHz
Signal to Noise Ratio, SINAD
RMS Signal
=
RMS Noise + Distortion
fS = 25MHz, fIN = 100kHz
fS = 25MHz, fIN = 5MHz
Total Harmonic Distortion, THD
Effective Number of Bits, ENOB
ANALOG INPUTS
fS = 25MHz, fIN = 100kHz
fS = 25MHz, fIN = 5MHz
fS = 25MHz, fIN = 100kHz
fS = 25MHz, fIN = 5MHz
Input Range
Full Scale Input Range
(Notes 1, 4)
Input Loading
Input Capacitance
Input Current
VIN = 2V (Note 2)
MIN
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
-
-
TYP MAX UNITS
-
±0.1
±0.125
±0.1
±0.125
-
-
-
-
-
±0.125
±0.25
±0.125
±0.25
±0.75
±1.0
±0.75
±1.0
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
3 - ns
23.7 - dB
23.6 - dB
23.4 - dB
22.8 - dB
-34.5 - dBc
-31.0 - dBc
3.67 - Bits
3.57 - Bits
- VAA V
10 - pF
150 200 µA
4-8









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CA3304 Даташит, Описание, Даташиты
CA3304, CA3304A
Electrical Specifications TA = 25oC, VREF+ = 2V, VDD = VAA+ = 5V, VAA- = VREF- = VSS = GND, fCLK = 25MHz
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNITS
Allowable Input Bandwidth
-3dB Input Bandwidth
(Note 4)
-
25
fCLK/2
MHz
- 40 - MHz
REFERENCE INPUTS
Input Range
Input Loading
DIGITAL INPUTS
VREF+ Range
VREF- Range
Resistor Ladder Impedance
(Note 4)
VAA- +0.5
-
VAA+
V
(Note 4)
VAA-
- VAA+ -0.5 V
VIN = 5V, CLK = Low 640 - 960
Digital Input
Maximum VIN, Low
CLOCK
CE1, CE2
Minimum VIN, High
CLOCK
CE1, CE2
Input Leakage, Except CLK
(Notes 3, 4)
(Note 4)
(Notes 3, 4)
(Note 4)
V = 0V, 5V
- - 0.3 x VAA V
- - 0.3 x VDD V
0.7 x VAA
-
-V
0.7 x VDD
-
-V
- - ±1 µA
Input Leakage, CLK
(Note 3)
-
±100
±150
µA
DIGITAL OUTPUTS
Digital Outputs
Output Low (Sink) Current
Output High (Source) Current
Three-State Leakage Current
TIMING CHARACTERISTICS
VO = 0.4V
VO = 4.6V
VO = 0V, 5V
6 - - mA
-3 -
- mA
- ±0.2 ±5 µA
Conversion Timing
Maximum Conversion Speed
Auto-Balance Time (φ1)
CLK = Square Wave
25 35
20 -
- MSPS
- ns
Sample Time (φ2)
20
-
5000
ns
Output Timing
Data Valid Delay
(Note 4)
- 30 40 ns
Data Hold Time
(Note 4)
15 25
- ns
Output Enable Time
- 15 - ns
Output Disable Time
- 10 - ns
POWER SUPPLY CHARACTERISTICS
Device Current, IAA
Continuous Clock
Continuous φ2
Continuous φ1
- 5.5 - mA
- 0.4 - mA
- 2 - mA
Device Current, IDD
VAA+ = 5V,
VSS = CE1 = VAA- = CLK = GND
VAA+ = 7V
Continuous Clock
Continuous φ2
Continuous φ1
- 1.5 - mA
- 5 10 mA
- 5 20 mA
NOTES:
1. Full scale input range, VREF+ - VREF-, may be in the range of 0.5V to VAA+ -VAA- volts. Linearity errors increase at lower full scale ranges,
however.
2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD
voltage.
3. The CLK input is a CMOS inverter with a 50kfeedback resistor. It operates from the VAA+ and VAA- supplies. It may be AC-coupled
with a 1VP-P minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
4-9










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