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HPC46104 PDF даташит

Спецификация HPC46104 изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «(HPC46164 / HPC36164 / HPC46104 / HPC36104) High-Performance microController with A/D».

Детали детали

Номер произв HPC46104
Описание (HPC46164 / HPC36164 / HPC46104 / HPC36104) High-Performance microController with A/D
Производители National Semiconductor
логотип National Semiconductor логотип 

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HPC46104 Даташит, Описание, Даташиты
January 1993
HPC36164 46164 HPC36104 46104
High-Performance microController with A D
General Description
The HPC46164 and HPC46104 are members of the HPCTM
family of High Performance microControllers Each member
of the family has the same core CPU with a unique memory
and I O configuration to suit specific applications The
HPC46164 has 16k bytes of on-chip ROM The HPC46104
has no on-chip ROM and is intended for use with external
memory Each part is fabricated in National’s advanced
microCMOS technology This process combined with an ad-
vanced architecture provides fast flexible I O control effi-
cient data manipulation and high speed computation
The HPC devices are complete microcomputers on a single
chip All system timing internal logic ROM RAM and I O
are provided on the chip to produce a cost effective solution
for high performance applications On-chip functions such
as UART up to eight 16-bit timers with 4 input capture regis-
ters vectored interrupts WATCHDOGTM logic and MICRO-
WIRE PLUSTM provide a high level of system integration
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips The term ‘‘HPC46164’’ is used throughout this data-
sheet to refer to the HPC46164 and HPC46104 devices un-
less otherwise specified
The HPC46164 and HPC46104 have as an on-board pe-
ripheral an 8-channel 8-bit Analog-to-Digital Converter This
A D converter can operate in a single-ended mode where
the analog input voltage is applied across one of the eight
input channels (D0–D7) and AGND The A D converter can
also operate in differential mode where the analog input
voltage is applied across two adjacent input channels The
A D converter will convert up to eight channels in single-
ended mode and up to four channel pairs in differential
mode
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings The HPC is available only in an
80-pin PQFP package
Features
Y HPC family core features
16-bit architecture both byte and word
16-bit data bus ALU and registers
64k bytes of external direct memory addressing
FAST 200 ns for fastest instruction when using
20 0 MHz clock 134 ns at 30 0 MHz
High code efficiency most instructions are single
byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters with 4 synchronous out-
puts and WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS very low power with two power save modes
IDLE and HALT
Y A D 8-channel 8-bit analog-to-digital converter with
g LSB non-linearity
Y UART full duplex programmable baud rate
Y Four additional 16-bit timer counters with pulse width
modulated outputs
Y Four input capture registers
Y 52 general purpose I O lines (memory mapped)
Y 16k bytes of ROM 512 bytes of RAM on-chip
Y ROMless version available (HPC46104)
Y Commercial (0 C to a70 C) and industrial (b40 C to
a85 C) temperature ranges
Block Diagram (HPC46164 with 16k ROM shown)
Series 32000 and TRI-STATE are registered trademarks of National Semiconductor Corporation
MOLETM HPCTM COPSTM microcontrollers WATCHDOGTM and MICROWIRE PLUSTM are trademarks of National Semiconductor Corporation
PC-AT is a registered trademark of International Business Machines Corp
SunOSTM is a trademark of Sun Microsystems
C1995 National Semiconductor Corporation TL DD 9682
TL DD 9682 – 1
RRD-B30M105 Printed in U S A









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HPC46104 Даташит, Описание, Даташиты
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b65 C to a150 C
Lead Temperature (Soldering 10 sec )
300 C
VCC with Respect to GND
b0 5V to 7 0V
All Other Pins
(VCC a 0 5)V to (GND b 0 5)V
Note Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
VCC e 5 0V g10% unless otherwise specified TA e 0 C to a70 C for HPC46164 HPC46104 b40 C to a85 C for
HPC36164 HPC36104
Symbol
Parameter
Test Conditions
Min Max Units
ICC1
Supply Current
VCC e 5 5V fin e 30 MHz (Note 1)
VCC e 5 5V fin e 20 MHz (Note 1)
VCC e 5 5V fin e 2 0 MHz (Note 1)
ICC2
IDLE Mode Current
VCC e 5 5V fin e 30 MHz (Note 1)
VCC e 5 5V fin e 20 MHz (Note 1)
VCC e 5 5V fin e 2 0 MHz (Note 1)
ICC3
HALT Mode Current
VCC e 5 5V fin e 0 kHz (Note 1)
VCC e 2 5V fin e 0 kHz (Note 1)
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET NMI WO AND ALSO CKI
65 mA
47 mA
10 mA
5 mA
3 mA
1 mA
300 mA
100 mA
VIH1
Logic High
VIL1 Logic Low
ALL OTHER INPUTS
0 9 VCC
0 1 VCC
V
V
VIH2
Logic High (except Port D)
VIL2 Logic Low (except Port D)
VIH3
Logic High (Port D Only)
VIL3 Logic Low (Port D Only)
ILI1 Input Leakage Current
ILI2 Input Leakage Current RDY HLD EXUI
ILI3 Input Leakage Current B12
CI Input Capacitance
CIO I O Capacitance
OUTPUT VOLTAGE LEVELS
(Note 9 in AC Characteristics)
(Note 9 in AC Characteristics)
VIN e 0 and VIN e VCC
VIN e 0
RESET e 0 VIN e VCC
(Note 2)
(Note 2)
0 7 VCC
0 7 VCC
b3
05
0 2 VCC
0 2 VCC
g2
b50
7
10
20
V
V
V
V
mA
mA
mA
pF
pF
VOH1 Logic High (CMOS)
IOH e b10 mA (Note 2)
VCC b 0 1
V
VOL1 Logic Low (CMOS)
IOH e 10 mA (Note 2)
01 V
VOH2
VOL2
Port A B Drive CK2
(A0 – A15 B10 B11 B12 B15)
IOH e b7 mA
IOL e 3 mA
24 V
04 V
VOH3
VOL3
Other Port Pin Drive WO (open
drain) (B0 – B9 B13 B14 P0 – P3)
IOH e b1 6 mA (except WO)
IOL e 0 5 mA
24 V
04 V
VOH4 ST1 and ST2 Drive
IOH e b6 mA
24 V
VOL4
IOL e 1 6 mA
04 V
VOH5
VOL5
Port A B Drive (A0 – A15 B10 B11 B12 B15) When
Used as External Address Data Bus
IOH e b1 mA
IOL e 3 mA
24 V
04 V
VRAM RAM Keep-Alive Voltage
(Note 3)
2 5 VCC V
IOZ TRI-STATE Leakage Current
VIN e 0 and VIN e VCC
g5 mA
Note 1 ICC1 ICC2 ICC3 measured with no external drive (IOH and IOL e 0 IIH and IIL e 0) ICC1 is measured with RESET e GND ICC3 is measured with NMI e
VCC and A D inactive CKI driven to VIH1 and VIL1 with rise and fall times less than 10 ns VREF e AGND e GND
Note 2 This is guaranteed by design and not tested
Note 3 Test duration is 100 ms
2









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HPC46104 Даташит, Описание, Даташиты
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) VCC e 5V g10% TA e 0 C to a70 C for HPC46164 and b40 C to
a85 C for HPC36164
Symbol and Formula
Parameter
Min Max Units
Notes
fC
tC1 e 1 fC
tCKIH
tCKIL
tC e 2 fC
tWAIT e tC
tDC1C2R
tDC1C2F
fU e fC 8
fMW
fXIN e fC 22
tXIN e tC
CKI Operating Frequency
CKI Clock Period
CKI High Time
CKI Low Time
CPU Timing Cycle
CPU Wait State Period
Delay of CK2 Rising Edge after CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
External UART Clock Input Frequency
External MICROWIRE PLUS Clock Input Frequency
External Timer Input Frequency
Pulse Width for Timer Inputs
2
50
22 5
22 5
100
100
0
0
100
20
500
55
55
25
1 25
0 91
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
(Note 2)
(Note 2)
tUWS
MICROWIRE Setup Time
Master
Slave
100
20
ns
tUWH
MICROWIRE Hold Time
Master
Slave
20
50
ns
tUWV
MICROWIRE Output Valid Time
Master
Slave
50
150
ns
tSALE e tC a 40
tHWP e tC a 10
tHAE e tC a 100
tHAD e tC a 85
tBF e tC a 66
tBE e tC a 66
tUAS
tUAH
tRPW
tOE
tOD
tDRDY
tWDW
tUDS
tUDH
tA
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
115 ns
110 ns
200 ns (Note 3)
160 ns
116 ns (Note 5)
116 ns (Note 5)
10 ns
10 ns
100 ns
0 60 ns
5 35 ns (Note 6)
70 ns
40 ns
10 ns
20 ns
70 ns
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
3










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