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74LVT125 PDF даташит

Спецификация 74LVT125 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «3.3V Quad buffer 3-State».

Детали детали

Номер произв 74LVT125
Описание 3.3V Quad buffer 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVT125 Даташит, Описание, Даташиты
74LVT125
3.3 V quad buffer; 3-state
Rev. 05 — 10 February 2005
Product data sheet
1. General description
The LVT125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The
device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one
of the 3-state outputs.
2. Features
s Quad bus interface
s 3-state buffers
s Output capability: +64 mA and 32 mA
s TTL input and output switching levels
s Input and output interface capability to systems at 5 V supply
s Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s No bus current loading when output is tied to 5 V bus
s Power-up 3-state
s Latch-up protection:
x JESD78: exceeds 500 mA
s ESD protection:
x MIL STD 883 method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C.
Symbol Parameter
Conditions
tPLH propagation delay nA to nY CL = 50 pF; VCC = 3.3 V
tPHL propagation delay nA to nY CL = 50 pF; VCC = 3.3 V
CI input capacitance
VI = 0 V or 3.0 V
CO output capacitance
outputs disabled;
VO = 0 V or 3.0 V
ICC quiescent supply current outputs disabled;
VCC = 3.6 V
Min Typ Max Unit
- 2.7 - ns
- 2.9 - ns
- 4 - pF
- 8 - pF
- 0.13 - mA









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74LVT125 Даташит, Описание, Даташиты
Philips Semiconductors
74LVT125
3.3 V quad buffer; 3-state
4. Ordering information
Table 2: Ordering information
Type number Package
Temperature range Name
Description
Version
74LVT125D 40 °C to +85 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVT125DB 40 °C to +85 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVT125PW 40 °C to +85 °C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVT125BQ 40 °C to +85 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 leads terminals;
body 2.5 × 3 × 0.85 mm
5. Functional diagram
2 1A
1Y 3
1 1OE
5 2A
2Y 6
4 2OE
9 3A
3Y 8
10 3OE
12 4A
4Y 11
13 4OE
mna228
Fig 1. Logic symbol
nA
Fig 3. Logic diagram
nOE
21
1 EN1
5
4
3
6
9
8
10
12
11
13
mna229
Fig 2. IEC logic symbol
nY
mna227
9397 750 14703
Product data sheet
Rev. 05 — 10 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 15









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74LVT125 Даташит, Описание, Даташиты
Philips Semiconductors
6. Pinning information
6.1 Pinning
74LVT125
3.3 V quad buffer; 3-state
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
125 11 4Y
10 3OE
9 3A
8 3Y
001aac476
Fig 4. Pin configuration SO14, SSOP14
and TSSOP14
terminal 1
index area
1A 2
1Y 3
2OE 4
2A 5
2Y 6
125
GND(1)
13 4OE
12 4A
11 4Y
10 3OE
9 3A
001aac477
Transparent top view
(1) The die substrate is attached to the
exposed die pad using conductive die
attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 3:
Symbol
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
1 output enable input (active LOW)
1 data input
1 data output
2 output enable input (active LOW)
2 data input
2 data output
ground (0 V)
3 data output
3 data input
3 output enable input (active LOW)
4 data output
4 data input
4 output enable input (active LOW)
supply voltage
9397 750 14703
Product data sheet
Rev. 05 — 10 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
3 of 15










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