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PDF 74LVT373 Data sheet ( Hoja de datos )
| Número de pieza | 74LVT373 | |
| Descripción | Low Voltage Octal Transparent Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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September 1999
Revised October 1999
74LVT373 • 74LVTH373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in a high impedance state.
The LVTH373 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH373), also
available without bushold feature (74LVT373).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 373
Ordering Code:
Order Number
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012015
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
tPHL Propagation Delay
tPLH
Dn to On
tPHL Propagation Delay
tPLH
LE to On
tPZL Output Enable Time
tPZH
tPLZ Output Disable Time
tPHZ
tW LE Pulse Width
tS Setup Time, Dn to LE
tH Hold Time, Dn to LE
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
Capacitance (Note 11)
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
VCC = 3.3V ±0.3V
VCC = 2.7V
Min
Typ
(Note 10)
Max
Min
Max
1.5 4.5 1.5 5.0
1.5 4.5 1.5 4.9
1.7 4.6 1.7 4.9
1.7 4.5 1.7 5.0
1.3 4.8 1.3 5.9
1.3 4.8 1.3 5.5
1.9 4.6 1.9 4.9
1.9 4.6 1.9 4.9
3.0 3.0
1.1 1.0
1.4 1.4
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = OPEN, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO= 0V or VCC
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
3
5
Units
ns
ns
ns
ns
ns
ns
ns
Units
pF
pF
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74LVT373.PDF ] | |
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