PDF W77C58 Data sheet ( Hoja de datos )

Número de pieza	W77C58
Descripción	8 BIT MICROCONTROLLER
Fabricantes	Winbond
Logotipo
Hay una vista previa y un enlace de descarga de W77C58 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas
No Preview Available ! Preliminary W77C58 8 BIT MICROCONTROLLER GENERAL DESCRIPTION The W77C58 is a fast 8051 compatible microcontroller with a redesigned processor core without wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the original 8051 for the same crystal speed. Typically, the instruction executing time of W77C58 is 1.5 to 3 times faster then that of traditional 8051, depending on the type of instruction. In general, the overall performance is about 2.5 times better than the original for the same crystal speed. Giving the same throughput with lower clock speed, power consumption has been improved. Consequently, the W77C58 is a fully static CMOS design; it can also be operated at a lower crystal clock. The W77C58 provides operating voltage from 4.5V to 5.5V. All W77C58 types also support on-chip 1KB SRAM without external memory component and glue logic, saving more I/O pins for users application usage if they use on-chip SRAM instead of external SRAM. FEATURES • 8-bit CMOS microcontroller • High speed architecture of 4 clocks/machine cycle runs up to 40 MHz • Pin compatible with standard 80C52 • Instruction-set compatible with MCS-51 • 32KB on-chip Mask-ROM • Four 8-bit I/O Ports • One extra 4-bit I/O port and Wait State control signal (available on 44-pin PLCC/QFP package) • Three 16-bit Timers • 12 interrupt sources with two levels of priority • On-chip oscillator and clock circuitry • Two enhanced full duplex serial ports • 256 bytes scratch-pad RAM • 1KB on-chip SRAM for MOVX instruction • Programmable Watchdog Timer • Dual 16-bit Data Pointers • Software programmable access cycle to external RAM/peripherals • Packages: − DIP 40: W77C58-25/40 − PLCC 44: W77C58P-25/40 − QFP 44: W77C58F-25/40 Publication Release Date: September 1999 - 1 - Revision A1 1 page Preliminary W77C58 data memory) between two machine cycles and nine machine cycles. This flexibility allows the W77C58 to work efficiently with both fast and slow RAMs and peripheral devices. In addition, the W77C58 contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and 03FFH. It only can be accessed by MOVX instruction; this on-chip SRAM is optional under software control. The W77C58 is an 8052 compatible device that gives the user the features of the original 8052 device, but with improved speed and power consumption characteristics. It has the same instruction set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). While the original 8051 family was designed to operate at 12 clock periods per machine cycle, the W77C58 operates at a much reduced clock rate of only 4 clock periods per machine cycle. This naturally speeds up the execution of instructions. Consequently, the W77C58 can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since the W77C58 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving the same throughput in terms of instruction execution, yet reducing the power consumption. The 4 clocks per machine cycle feature in the W77C58 is responsible for a three-fold increase in execution speed. The W77C58 has all the standard features of the 8052, and has a few extra peripherals and features as well. I/O Ports The W77C58 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data bus when external program is running or external memory/device is accessed by MOVC or MOVX instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull- ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong pull-ups and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate functions. Port 4 is only available on 44-pin PLCC/QFP package type. It serves as a general purpose I/O port as Port 1 and Port 3. The P4.0 has an alternate function WAIT that is the wait state control signal. When wait state control signal is enabled, P4.0 is input only. Serial I/O The W77C58 has two enhanced serial ports that are functionally similar to the serial port of the original 8052 family. However the serial ports on the W77C58 can operate in different modes in order to obtain timing similarity as well. Note that the serial port 0 can use Timer 1 or 2 as baud rate generator, but the serial port 1 can only use Timer 1 as baud rate generator. The serial ports have the enhanced features of Automatic Address recognition and Frame Error detection. Timers The W77C58 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the user with the option of operating in a mode that emulates the timing of the original 8052. The W77C58 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as a very long time period timer. Interrupts The Interrupt structure in the W77C58 is slightly different from that of the standard 8052. Due to the presence of additional features and peripherals, the number of interrupt sources and vectors has been increased. The W77C58 provides 12 interrupt resources with two-priority level, including six external interrupt sources, timer interrupts, serial I/O interrupts and power-fail interrupt. Publication Release Date: September 1999 - 5 - Revision A1 5 Page Preliminary W77C58 IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. IT1: Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. IE0: Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the pin. IT0: Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered external inputs. Timer Mode Control Bit: 7 6 5 4 3 2 1 0 GATE C/ T M1 M0 GATE C/ T M1 M0 Mnemonic: TMOD TIMER1 TIMER0 Address: 89h GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. C/ T : Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set, the timer counts high-to-low edges of the Tx pin. M1, M0: Mode Select bits: M1 M0 00 01 10 11 Mode Mode 0: 8-bits with 5-bit prescale. Mode 1: 18-bits, no prescale. Mode 2: 8-bits with auto-reload from THx Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1) Timer/counter is stopped. Timer 0 LSB Bit: 7 6 5 4 3 2 1 0 TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Mnemonic: TL0 Address: 8Ah TL0.7-0:Timer 0 LSB - 11 - Publication Release Date: September 1999 Revision A1 11 Page

Páginas	Total 70 Páginas
PDF Descargar	[ Datasheet W77C58.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
W77C58	8 BIT MICROCONTROLLER	Winbond

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar