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PDF ISL6227 Data sheet ( Hoja de datos )
| Número de pieza | ISL6227 | |
| Descripción | Dual Mobile-Friendly PWM Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
May 4, 2009
ISL6227
FN9094.7
Dual Mobile-Friendly PWM Controller with
DDR Option
The ISL6227 dual PWM controller delivers high efficiency
precision voltage regulation from two synchronous buck DC/DC
converters. It was designed especially to provide power
regulation for DDR memory, chipsets, graphics and other
system electronics in Notebook PCs. The ISL6227’s wide
input voltage range capability allows for voltage conversion
directly from AC/DC adaptor or Li-Ion battery pack.
Automatic mode transition of constant-frequency synchronous
rectification at heavy load, and hysteretic (HYS)
diode-emulation at light load, assure high efficiency over a wide
range of conditions. The HYS mode of operation can be
disabled separately on each PWM converter if
constant-frequency continuous-conduction operation is desired
for all load levels. Efficiency is further enhanced by using the
lower MOSFET rDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, current mode
control, and internal feedback compensation provide fast
response to input voltage and load transients. Input current
ripple is minimized by channel-to-channel PWM phase shift
of 0°, 90° or 180° (determined by input voltage and status of
the DDR pin).
The ISL6227 can control two independent output voltages
adjustable from 0.9V to 5.5V, or by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory.
The reference voltage VREF required by DDR memory is
generated as well.
In dual power supply applications the ISL6227 monitors the
output voltage of both CH1 and CH2. An independent PGOOD
(power good) signal is asserted for each channel after the
soft-start sequence has completed, and the output voltage is
within PGOOD window. In DDR mode CH1 generates the only
PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage re-enters
regulation, PGOOD will go HIGH and normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage
drop across the rDS(ON) of the lower MOSFET. If more precise
current-sensing is required, an external current sense resistor
may be used.
Features
• Provides Regulated Output Voltage in the Range 0.9V to
5.5V
• Operates From an Input Battery Voltage Range of 5V to
28V or From 3.3V/5V System Rail
• Complete DDR1 and DDR2 Memory Power Solution with
VTT Tracking VDDQ/2 and a VDDQ/2 Buffered Reference
Output
• Flexible PWM or HYS Plus PWM Mode Selection with
HYS Diode Emulation at Light Loads for Higher System
Efficiency
• rDS(ON) Current Sensing
• Excellent Dynamic Response With Voltage Feed-Forward
and Current Mode Control Accommodating Wide Range
LC Filter Selections
• Undervoltage Lock-Out on VCC Pin
• Power-Good, Overcurrent, Overvoltage, Undervoltage
Protection for Both Channels
• Synchronized 300kHz PWM Operation in PWM Mode
• Pb-Free Available (RoHS compliant)
Applications
• Notebook PCs and Desknotes
• Tablet PCs/Slates
• Hand-Held Portable Instruments
Ordering Information
PART
PART
TEMP.
PKG.
NUMBER MARKING RANGE (°C) PACKAGE DWG. #
ISL6227CA* ISL 6227CA -10 to +100 28 Ld QSOP M28.15
ISL6227CAZ* ISL 6227CAZ -10 to +100 28 Ld QSOP M28.15
(Note)
(Pb-Free)
ISL6227IA* ISL 6227IA -40 to +100 28 Ld QSOP M28.15
ISL6227IAZ* ISL 6227IAZ -40 to +100 28 Ld QSOP M28.15
(Note)
(Pb-Free)
ISL6227HRZ* ISL 6227HRZ -10 to +100 28 Ld QFN L28.5x5
(Note)
(Pb-Free)
ISL6227IRZ* ISL 6227IRZ -40 to +100 28 Ld QFN L28.5x5
(Note)
(Pb-Free)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6227
Typical Operation Performance
100
EFF@ 5V
90
EFF@ 12V
80
70 EFF@ 5V, PWM
60
50
EFF@ 19.5V
EFF@ 12V, PWM
40
30
20 EFF@ 19.5V, PWM
10
0
0.01
0.10
1.00
LOAD CURRENT (A)
10.0
FIGURE 1. EFFICIENCY OF CHANNEL 1, 2.5V,
HYS/PWM MODE
100
EFF@ 12V
90
80
70
EFF@ 5V
60
EFF@ 19.5V
EFF@ 19.5V, PWM
50
EFF@ 12V, PWM
40
EFF@ 5V, PWM
30
20
10
0
0.01
0.10
1.00
LOAD CURRENT (A)
10.0
FIGURE 2. EFFICIENCY OF CHANNEL 2, 1.8V,
HYS/PWM MODE
2.54
2.53
VOUT @ 19.5V
2.52
2.51
2.50
VOUT @ 12V
VOUT @ 19.5V, PWM
2.49
2.48
2.47
0
VOUT @ 5V, PWM
VOUT @ 5V
VOUT @ 12V, PWM
123
LOAD CURRENT (A)
4
5
FIGURE 3. OUTPUT VOLTAGE OF CHANNEL 1 vs LOAD
308
306
304
302
300
298
296
294
292
290
288
286
-20
0
75% QUANTILE
FREQUENCY MEAN
25% QUANTILE
20 40 60 80
TEMPERATURE (°C)
100 120
FIGURE 5. SWITCHING FREQUENCY OVER-TEMPERATURE
5
1.83
VOUT @ 19.5V
1.82
VOUT @ 12V
1.81
1.80
VOUT @ 12V, PWM
VOUT @ 19.5V, PWM
1.79
1.78
0
VOUT @ 5V, PWM
VOUT @ 5V
12 3
LOAD CURRENT (A)
4
5
FIGURE 4. OUTPUT VOLTAGE OF CHANNEL 2 vs LOAD
0.9025
0.9020
0.9015
0.9010
0.9005
0.9000
0.8995
0.8990
0.8985
75% QUANTILE
VREF MEAN
25% QUANTILE
0.8980
0.8975
-20
0
20 40 60 80
TEMPERATURE (°C)
100
FIGURE 6. REFERENCE VOLTAGE ACCURACY
OVER-TEMPERATURE
120
FN9094.7
May 4, 2009
5 Page 
ISL6227
PG2/REF
This pin has a double function, depending on the mode of
operation.
When the chip is used as a dual channel PWM controller
(DDR = 0), the pin provides an open drain PGOOD2 function
for the second channel the same way as PG1. The pin is
pulled low when the second channel output is out of
-11% to +15% of the set value.
In DDR mode (DDR = 1), this pin is the output of the buffer
amplifier that takes VDDQ/2 voltage applied to OCSET2 pin
from the resister divider. It can source a typical 10mA
current.
OCSET2
In a dual channel application with DDR = 0, a resistor from
this pin to ground sets the overcurrent threshold for the
second channel controller. Its voltage is the buffered internal
0.9V reference.
In the DDR application with DDR = 1, this pin connects to the
center point of a resistor divider tracking the VDDQ/2. This
voltage is then buffered by an amplifier voltage follower and
sent to the PG2/REF pin. It sets the reference voltage of
Channel 2 for its regulation.
VCC
This pin powers the controller.
Typical Application
Figures 31 and 32 show the application circuits of a dual
channel DC/DC converter for a notebook PC.
The power supply in Figure 31 provides +2.5V and +1.8V
voltages for memory and the graphics interface chipset from
a +5.0VDC to a 28VDC battery voltage.
Figure 32 illustrates the application circuit for a DDR memory
power solution. The power supply shown in Figure 32
generates +2.5V VDDQ voltage from a battery. The +1.25V
VTT termination voltage tracks VDDQ/2 and is derived from
+2.5V VDDQ. To complete the DDR memory power
requirements, the +1.25V reference voltage is provided
through the PG2 pin.
11 FN9094.7
May 4, 2009
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ISL6227.PDF ] | |
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