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PDF 82801DB Data sheet ( Hoja de datos )

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Descripción I/O Controller Hub 4
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Intel® 82801DB I/O Controller
Hub 4 (ICH4)
Datasheet
May 2002
Document Number: 290744-001

1 page




82801DB pdf
Contents
1 Introduction...........................................................................................................27
1.1 About This Datasheet ....................................................................................27
1.2 Overview ........................................................................................................30
2 Signal Description ..............................................................................................37
2.1 Hub Interface to Host Controller ....................................................................39
2.2 Link to LAN Connect ......................................................................................39
2.3 EEPROM Interface ........................................................................................40
2.4 Firmware Hub Interface .................................................................................40
2.5 PCI Interface ..................................................................................................40
2.6 IDE Interface ..................................................................................................43
2.7 LPC Interface .................................................................................................44
2.8 Interrupt Interface...........................................................................................44
2.9 USB Interface.................................................................................................45
2.10 Power Management Interface........................................................................46
2.11 Processor Interface........................................................................................47
2.12 SMBus Interface ............................................................................................48
2.13 System Management Interface ......................................................................48
2.14 Real Time Clock Interface..............................................................................49
2.15 Other Clocks ..................................................................................................49
2.16 Miscellaneous Signals ...................................................................................49
2.17 AC-Link ..........................................................................................................50
2.18 General Purpose I/O ......................................................................................51
2.19 Power and Ground.........................................................................................52
2.20 Pin Straps ......................................................................................................53
2.20.1 Functional Straps ..............................................................................53
2.20.2 External RTC Circuitry ......................................................................54
2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................54
2.20.4 Test Signals ......................................................................................55
3 Intel® ICH4 Power Planes and Pin States .................................................57
3.1 Power Planes.................................................................................................57
3.2 Integrated Pull-Ups and Pull-Downs ..............................................................58
3.3 IDE Integrated Series Termination Resistors.................................................58
3.4 Output and I/O Signals Planes and States ....................................................59
3.5 Power Planes for Input Signals......................................................................63
4 Intel® ICH4 and System Clock Domains....................................................65
5 Functional Description .....................................................................................67
5.1 Hub Interface to PCI Bridge (D30:F0)............................................................67
5.1.1 PCI Bus Interface..............................................................................67
5.1.2 PCI-to-PCI Bridge Model ..................................................................68
5.1.3 IDSEL to Device Number Mapping ...................................................68
5.1.4 SERR# Functionality.........................................................................68
5.1.5 Parity Error Detection........................................................................70
5.1.6 Standard PCI Bus Configuration Mechanism ...................................71
5.1.7 PCI Dual Address Cycle (DAC) Support...........................................72
Intel® 82801DB ICH4 Datasheet
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82801DB arduino
9.1.20 D31_ERR_STS—Device 31 Error Status Register
(LPC I/F—D31:F0) ..........................................................................300
9.1.21 PCI_DMA_CFG—PCI DMA Configuration (LPC I/F—D31:F0) ......301
9.1.22 GEN_CNTL — General Control Register (LPC I/F — D31:F0) ......302
9.1.23 GEN_STA—General Status Register (LPC I/F—D31:F0) ..............304
9.1.24 BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0) ..........................................................................304
9.1.25 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)......305
9.1.26 COM_DEC—LPC I/F Communication Port Decode Ranges
(LPC I/F—D31:F0) ..........................................................................305
9.1.27 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
(LPC I/F—D31:F0) ..........................................................................306
9.1.28 SND_DEC—LPC I/F Sound Decode Ranges
(LPC I/F—D31:F0) ..........................................................................306
9.1.29 FWH_DEC_EN1—FWH Decode Enable 1 Register
(LPC I/F—D31:F0) ..........................................................................307
9.1.30 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0) ..........................................................................308
9.1.31 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ...............308
9.1.32 FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0) ..............310
9.1.33 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0) ..........................................................................311
9.1.34 FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0) ..............311
9.1.35 FWH_DEC_EN2—FWH Decode Enable 2 Register
(LPC I/F—D31:F0) ..........................................................................312
9.1.36 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) ..........313
9.2 DMA I/O Registers .......................................................................................315
9.2.1 DMABASE_CA—DMA Base and Current Address Registers ........316
9.2.2 DMABASE_CC—DMA Base and Current Count Registers............316
9.2.3 DMAMEM_LP—DMA Memory Low Page Registers ......................317
9.2.4 DMACMD—DMA Command Register ............................................317
9.2.5 DMASTA—DMA Status Register ....................................................318
9.2.6 DMA_WRSMSK—DMA Write Single Mask Register ......................318
9.2.7 DMACH_MODE—DMA Channel Mode Register............................319
9.2.8 DMA Clear Byte Pointer Register ...................................................319
9.2.9 DMA Master Clear Register ............................................................320
9.2.10 DMA_CLMSK—DMA Clear Mask Register ....................................320
9.2.11 DMA_WRMSK—DMA Write All Mask Register ..............................320
9.3 Timer I/O Registers......................................................................................321
9.3.1 TCW—Timer Control Word Register ..............................................321
9.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ...........323
9.3.3 Counter Access Ports Register.......................................................323
9.4 8259 Interrupt Controller (PIC) Registers ....................................................324
9.4.1 ICW1—Initialization Command Word 1 Register ............................325
9.4.2 ICW2—Initialization Command Word 2 Register ............................326
9.4.3 ICW3—Master Controller Initialization Command Word 3 Register326
9.4.4 ICW3—Slave Controller Initialization Command Word 3 Register .327
9.4.5 ICW4—Initialization Command Word 4 Register ............................327
9.4.6 OCW1—Operational Control Word 1 (Interrupt Mask) Register .....327
9.4.7 OCW2—Operational Control Word 2 Register ...............................328
9.4.8 OCW3—Operational Control Word 3 Register ...............................328
9.4.9 ELCR1—Master Controller Edge/Level Triggered Register ...........329
Intel® 82801DB ICH4 Datasheet
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