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PDF HD64F2166 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2166 | |
| Descripción | (HD64F2166 - HD64F2168) Hardware Manual | |
| Fabricantes | Renesas Technology | |
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REJ09B0078-0300Z
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2168Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2168
H8S/2167
H8S/2166
HD64F2168
HD64F2167
HD64F2166
Rev.3.00
Revision Date: Mar. 12, 2004
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00, 03/04, page v of xl
5 Page 
5.4.1 External Interrupts ............................................................................................... 82
5.4.2 Internal Interrupts ................................................................................................ 84
5.5 Interrupt Exception Handling Vector Table...................................................................... 85
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 88
5.6.1 Interrupt Control Mode 0 ..................................................................................... 90
5.6.2 Interrupt Control Mode 1 ..................................................................................... 92
5.6.3 Interrupt Exception Handling Sequence .............................................................. 94
5.6.4 Interrupt Response Times .................................................................................... 96
5.6.5 DTC Activation by Interrupt................................................................................ 97
5.7 Usage Notes ...................................................................................................................... 99
5.7.1 Conflict between Interrupt Generation and Disabling ......................................... 99
5.7.2 Instructions that Disable Interrupts ...................................................................... 100
5.7.3 Interrupts during Execution of EEPMOV Instruction.......................................... 100
5.7.4 IRQ Status Registers (ISR16, ISR) ...................................................................... 100
Section 6 Bus Controller (BSC).........................................................................101
6.1 Features............................................................................................................................. 101
6.2 Input/Output Pins .............................................................................................................. 104
6.3 Register Descriptions ........................................................................................................ 105
6.3.1 Bus Control Register (BCR) ................................................................................ 105
6.3.2 Bus Control Register 2 (BCR2) ........................................................................... 106
6.3.3 Wait State Control Register (WSCR) .................................................................. 108
6.3.4 Wait State Control Register 2 (WSCR2) ............................................................. 110
6.4 Bus Control ....................................................................................................................... 112
6.4.1 Bus Specifications................................................................................................ 112
6.4.2 Advanced Mode................................................................................................... 122
6.4.3 I/O Select Signals................................................................................................. 123
6.5 Bus Interface ..................................................................................................................... 124
6.5.1 Data Size and Data Alignment............................................................................. 124
6.5.2 Valid Strobes ....................................................................................................... 126
6.5.3 Basic Operation Timing in Normal Extended Mode ........................................... 127
6.5.4 Basic Operation Timing in Address-Data Multiplex Extended Mode ................. 135
6.5.5 Wait Control ........................................................................................................ 141
6.6 Burst ROM Interface......................................................................................................... 145
6.6.1 Basic Operation Timing....................................................................................... 145
6.6.2 Wait Control ........................................................................................................ 146
6.7 Idle Cycle.......................................................................................................................... 147
6.8 Bus Arbitration.................................................................................................................. 148
6.8.1 Overview.............................................................................................................. 148
6.8.2 Operation ............................................................................................................. 148
6.8.3 Bus Mastership Transfer Timing ......................................................................... 148
Rev. 3.00, 03/04, page xi of xl
11 Page | ||
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