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82865GV PDF даташит

Спецификация 82865GV изготовлена ​​​​«Intel» и имеет функцию, называемую «Graphics and Memory Controller Hub».

Детали детали

Номер произв 82865GV
Описание Graphics and Memory Controller Hub
Производители Intel
логотип Intel логотип 

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82865GV Даташит, Описание, Даташиты
Intel® 865G/865GV Chipset
Datasheet
Intel® 82865G/82865GV Graphics and Memory Controller Hub
(GMCH)
February 2004
Document Number: 252514-005









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82865GV Даташит, Описание, Даташиты
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82865G/82865GV GMCH may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Imple-
mentations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corpora-
tion.
Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun-
tries.
*Other names and brands may be claimed as the property of others.
Copyright© 2003–2004, Intel Corporation
2 Intel® 82865G/82865GV GMCH Datasheet









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82865GV Даташит, Описание, Даташиты
Contents
1 Introduction...........................................................................................................15
1.1 Terminology ...................................................................................................16
1.2 Related Documents .......................................................................................17
1.3 Intel® 865G Chipset System Overview ..........................................................18
1.4 Intel® 82865G GMCH Overview ....................................................................20
1.4.1 Host Interface....................................................................................20
1.4.2 System Memory Interface .................................................................20
1.4.3 Hub Interface ....................................................................................21
1.4.4 Communications Streaming Architecture (CSA) Interface ................21
1.4.5 Multiplexed AGP and Intel® DVO Interface.......................................21
1.4.6 Graphics Overview............................................................................22
1.4.7 Display Interface ...............................................................................24
1.5 Clock Ratios...................................................................................................24
2 Signal Description ..............................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Host Interface Signals....................................................................................27
Memory Interface ...........................................................................................30
2.2.1 DDR SDRAM Channel A ..................................................................30
2.2.2 DDR SDRAM Channel B ..................................................................31
Hub Interface .................................................................................................32
Communication Streaming Architecture (CSA) Interface...............................32
AGP Interface ................................................................................................33
2.5.1 AGP Addressing Signals...................................................................33
2.5.2 AGP Flow Control Signals ................................................................34
2.5.3 AGP Status Signals ..........................................................................34
2.5.4 AGP Strobes .....................................................................................35
2.5.5 PCI Signals–AGP Semantics............................................................36
2.5.6
2.5.7
2.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........37
Multiplexed Intel® DVOs on AGP ......................................................37
Intel® DVO-to-AGP Pin Mapping.......................................................39
Analog Display Interface ................................................................................40
Clocks, Reset, and Miscellaneous Signals ....................................................41
RCOMP, VREF, VSWING Signals.................................................................42
Power and Ground Signals ............................................................................43
GMCH Sequencing Requirements.................................................................44
Signals Used As Straps .................................................................................45
2.11.1 Functional Straps ..............................................................................45
2.11.2 Strap Input Signals............................................................................45
Full and Warm Reset States ..........................................................................46
3 Register Description..........................................................................................47
3.1 Register Terminology.....................................................................................47
3.2 Platform Configuration Structure....................................................................48
3.3 Routing Configuration Accesses....................................................................50
3.3.1 Standard PCI Bus Configuration Mechanism ...................................50
3.3.2 PCI Bus #0 Configuration Mechanism ..............................................50
3.3.3 Primary PCI and Downstream Configuration Mechanism.................50
3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................51
Intel® 82865G/82865GV GMCH Datasheet
3










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Номер в каталогеОписаниеПроизводители
82865GGraphics and Memory Controller HubIntel
Intel
82865GVGraphics and Memory Controller HubIntel
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