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S3067TB20 PDF даташит

Спецификация S3067TB20 изготовлена ​​​​«Applied Micro Circuits» и имеет функцию, называемую «Multirate Sonet / SDH / ATM Transceiver w/FEC».

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Номер произв S3067TB20
Описание Multirate Sonet / SDH / ATM Transceiver w/FEC
Производители Applied Micro Circuits
логотип Applied Micro Circuits логотип 

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S3067TB20 Даташит, Описание, Даташиты
DEVICE
SMPUELCTIFIIRCAATTIEON(OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SMBOUiCNLMETIOTR/SASDTLEHVP/(AOETCCM-L48OC/C2L4-O1/1C22K/3T/GRGEABNEES/FRMCAI)TTSTOOERNREATN/SDDRHE/ACTEMIVTERRANSCEIVER w/ FEC
®
S3067
SS33006677
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock generation
• Supports:
- OC-48 (with FEC)
- OC-24 (with FEC)
- OC-12 (with FEC)
- OC-3 (with FEC)
- Fibre Channel
• FEC capability up to 8 bytes per 255-byte block
• Reference frequency – 131.25 MHz to 178 MHz
• Interface to LVPECL and TTL logic
• 16-Bit single-ended LVPECL data path
• Compact 156 Pin TBGA package
• Diagnostic loopback mode
• Supports line timing
• Lock Detect
• Signal detect input
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3 V supply
• Typical power 1.5 W
APPLICATIONS
• Wavelength Division Multiplexing equipment
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
131.25 MHz to 178 MHz reference clock in support
of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3067 is pack-
aged in a 156 Pin TBGA, offering designers a small
package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
Figure 1. System Block Diagram
2.488 Gbps
X
S3076
Clock
Recovery
Unit
2.488
Gbps
X
PERFORMANCE MONITOR
S3067
155 Mbps
Receive
Deserialization
X
S3062
Receive
S3062 167 Mbps S3067 2.67 Gbps
Transmit
FEC Added
X+Y
Transmit
Serialization X + Y
E/O
OPTICAL FIBER
PERFORMANCE MONITOR
O/E
S3076
S3067
S3062
Clock 2.67 Gbps Receive
167 Mbps Receive
Recovery X + Y Deserialization X + Y FEC Data
Unit Stripped Off
S3062
Transmit
155 Mbps
S3067
Transmit
2.488 Gbps
X Serialization X
X = Data
Y = FEC Data
September 17, 2002/ Revision A
1









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S3067TB20 Даташит, Описание, Даташиты
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SONET OVERVIEW
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
The SONET standard is a layered protocol with four
separate layers defined. These are:
• Photonic
• Section
• Line
• Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to op-
tical and back with no overhead. It is responsible
for transmitting the electrical signals in optical form
over the physical media. The section layer handles
Figure 2. SONET Structure
Functions
Payload to
SPE mapping
Path layer
Maintenance,
protection,
switching
Line layer
Scrambling, Section layer
framing
Path layer
Line layer
Section layer
Optical Photonic layer
transmission
Photonic layer
End Equipment
Fiber Cable
End Equipment
Figure 3. STS–48/OC–48 Frame Format
the transport of the framed electrical signals across
the optical cable from one end to the next. Key
functions of this layer are framing, scrambling, and
error monitoring. The line layer is responsible for
the reliable transmission of the path layer informa-
tion stream, carrying voice, data, and video signals.
Its main functions are synchronization, multiplexing,
and reliable transport. The path layer is responsible
for the actual transport of services at the appropri-
ate signaling rates.
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designa-
tions of the SONET hierarchy. The lowest level is the
basic SONET signal referred to as the synchronous
transport signal level-1 (STS-1). An STS-N signal is
made up of N-byte-interleaved STS-1 signals. The op-
tical counterpart of each STS-N signal is an optical
carrier level-N signal (OC-N). The S3067 chip sup-
ports up to the OC-48 rate with different FEC modes.
Frame and Byte Boundary Detection
The SONET/SDH fundamental frame format for
STS-48 consists of 144 transport overhead bytes
followed by Synchronous Payload Envelope (SPE)
bytes. This pattern of 144 overhead and 4176 SPE
bytes is repeated nine times in each frame. Frame and
byte boundaries are detected using the A1 and A2
bytes found in the transport overhead. (See Figure 3.)
For more details on SONET operations, refer to the
Bellcore SONET standard document.
Table 1. SONET Signal Hierarchy
Elec.
STS-1
STS-3
STS-12
STS-24
STS-48
CCITT
STM-1
STM-4
STM-8
STM-16
Optical
OC-1
OC-3
OC-12
OC-24
OC-48
Data Rate (Mbps)
51.84
155.52
622.08
1244.16
2488.32
A1 A1
A1 A1
48 A1
Bytes
A2 A2
A2 A2
48 A2
Bytes
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
125 µsec
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
2 September 17, 2002/ Revision A









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S3067TB20 Даташит, Описание, Даташиты
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
S3067
S3067 OVERVIEW
The S3067 transceiver implements SONET/SDH
and WDM serialization/deserialization, and transmis-
sion functions. The block diagram in Figure 4 shows
the basic operation of the chip. This chip can be
used to implement the front end of WDM equipment,
which consists primarily of the serial transmit inter-
face and the serial receive interface. The chip
handles all the functions of these two elements, in-
cluding parallel-to-serial and serial-to-parallel
conversion, clock generation, and system timing.
The system timing circuitry consists of management
of the data stream and clock distribution throughout
the front end.
S3067 has the ability to bypass the internal VCO
with an external source and also with the receive
clock. The device generates 14/15, 15/14, 16/17 and
17/16 clocks based upon the received clock and an
external clock to incorporate the FEC capability. The
dividers support the first two rates shown in Table 4.
The S3067 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Table 2. Data Rate Select
RATESEL 0 RATESEL 1 Operating Mode
0 0 OC-3
0 1 OC-12
1 0 OC-24/GBE/FC
1 1 OC-48
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. S3067 Supports six different code
rates, besides the normal rate, for each of the four
operating modes.
Suggested Interface Devices
AMCC S3076 OC-48 Clock Recovery Device
AMCC S3062 OC-48 Performance Monitor
Table 3. FEC Select
FEC 0
1
2
0 01
1 01
0 11
1 11
0 00
1 00
0 10
1 10
VCO
Divider
17
16
15
14
17
16
15
14
RSCLK
Divider
16
17
14
15
X
X
X
X
Table 4. FEC Modes
Error Correcting Capability
Code Rate showing
Bandwidth Expansion due
to code words & FSB
Example of increased input clock
frequency for STS-48/STM-16 (MHz)
8 bytes per 255-byte block
255/238 = 7.14% increase
155.52*255/238 = 155.52 * 15/14 = 166.63
7 bytes per 255-byte block
255/240 = 6.25% increase
155.52*255/240 = 155.52 * 17/16 = 165.24
6 bytes per 255-byte block
255/242 = 5.37% increase
155.52*255/242 = 163.87
5 bytes per 255-byte block
255/244 = 4.51% increase
155.52*255/244 = 162.53
4 bytes per 255-byte block
255/246 = 3.66% increase
155.52*255/246 = 155.52 * 85/82 = 161.21
3 bytes per 255-byte block
255/248 = 2.82% increase
155.52*255/248 = 159.91
September 17, 2002/ Revision A
3










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Номер в каталогеОписаниеПроизводители
S3067TB20Multirate Sonet / SDH / ATM Transceiver w/FECApplied Micro Circuits
Applied Micro Circuits

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