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Número de pieza | W83194BR-B | |
Descripción | Stepless Clock Gen For INTEL Brookdale Chipset | |
Fabricantes | Winbond | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de W83194BR-B (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
No Preview Available ! W83194BR-B
Stepless Clock Gen. For INTEL
Brookdale Chipset
Date: 02/25/2003 Revision: 2.0
1 page W83194BR-B
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
1. GENERAL DESCRIPTION
The W83194BR-B is a Clock Synthesizer for Intel Brook dale 845 chipset. W83194BR-B provides all
clocks required for high-speed microprocessor and provides step-less frequency programming and 32
different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are externally selectable with
smooth transitions.
The W83194BR-B provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T.
scale to reduce EMI.
The W83194BR-B also has watch dog timer and reset output pin to support auto-reset when systems
hanging caused by improper frequency setting.
The W83194BR-B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU
CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5%
duty cycle. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
• 3 pairs of CPU clock outputs
• 4 3V66 clock outputs
• 9 PCI synchronous clocks
• 2 48 MHz clock outputs for USB and DOT
• Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.6 to 200MHz
• Step-less frequency programming
• I2C 2-Wire serial interface and I2C read back
• -0.5% and +/- 0.25% center type spread spectrum
• Programmable S.S.T. scale to reduce EMI
• Programmable registers to enable/stop each output and select modes
• Watch Dog Timer and RESET# output pins
• 48-pin SSOP package
Publication Release Date: February 2003
- 1 - Revision 2.0
5 Page W83194BR-B
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0: Frequency Select Register (Default = 0)
Bit
Name
PWD Description
0 Enable Spread Spectrum in the frequency table.
7 EN_SPSP
0 = Normal
1 = Spread Spectrum enabled
6
SSEL [4]
0
5
SSEL [3]
0
4
SSEL [2]
0 Frequency selection by software via I2C.
3
SSEL [1]
0
2
SSEL [0]
0
0 Enable software program FS [4:0].
1 EN_SSEL
0 = Select frequency by hardware.
1= Select frequency by software I2C - Bit 6 ~ 2.
0 Enable reload safe frequency when the watchdog is timeout.
0 EN_SAFE_FREQ
0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 6 bit 4~0.
7.2 Register 1: CPU Clock Register (1 = Enable, 0 = Stopped)
Bit Pin NO PWD Description
7
47, 46
1 CPUCLKT2 / C2
6
44, 43
1 CPUCLKT1 / C1
5
40, 39
1 CPUCLKT0 / C0
4 - X FS [4] Read back.
3 - X FS [3] Read back
2 - X FS [2] Read back
1 - X FS [1] Read back
0 - X FS [0] Read back
7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Stopped)
Bit Pin NO PWD Description
7 - X MULTISEL0 trapping pin data read back
6 17 1 PCICLK 6
5 16 1 PCICLK 5
4 15 1 PCICLK 4
3 12 1 PCICLK 3
2 11 1 PCICLK 2
1 10 1 PCICLK 1
0 9 1 PCICLK 0
Publication Release Date: February 2003
- 7 - Revision 2.0
11 Page |
Páginas | Total 19 Páginas | |
PDF Descargar | [ Datasheet W83194BR-B.PDF ] |
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