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PDF HD6433692G Data sheet ( Hoja de datos )
| Número de pieza | HD6433692G | |
| Descripción | (HD64xxxx Series) 16-BIT MICROCONTROLLER | |
| Fabricantes | Renesas Technology | |
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REJ09B0028-0400Z
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8/3694Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/3694N
H8/3694F
H8/3694
H8/3693
H8/3692
H8/3691
H8/3690
HD64N3694G, HD6483694G,
HD64F3694, HD64F3694G,
HD6433694, HD6433694G,
HD6433693, HD6433693G,
HD6433692, HD6433692G,
HD6433691, HD6433691G,
HD6433690, HD6433690G
Rev.4.00
Revision Date: Mar. 18, 2004
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 4.00, 03/04, page v of xxviii
5 Page 
6.3 Operating Frequency in Active Mode............................................................................... 82
6.4 Direct Transition ............................................................................................................... 82
6.4.1 Direct Transition from Active Mode to Subactive Mode .................................... 82
6.4.2 Direct Transition from Subactive Mode to Active Mode .................................... 83
6.5 Module Standby Function................................................................................................. 83
Section 7 ROM ..................................................................................................85
7.1 Block Configuration.......................................................................................................... 85
7.2 Register Descriptions ........................................................................................................ 86
7.2.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 87
7.2.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 88
7.2.3 Erase Block Register 1 (EBR1) ........................................................................... 88
7.2.4 Flash Memory Power Control Register (FLPWCR) ............................................ 89
7.2.5 Flash Memory Enable Register (FENR) .............................................................. 89
7.3 On-Board Programming Modes........................................................................................ 90
7.3.1 Boot Mode ........................................................................................................... 90
7.3.2 Programming/Erasing in User Program Mode..................................................... 93
7.4 Flash Memory Programming/Erasing ............................................................................... 94
7.4.1 Program/Program-Verify ..................................................................................... 94
7.4.2 Erase/Erase-Verify............................................................................................... 96
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 97
7.5 Program/Erase Protection ................................................................................................. 99
7.5.1 Hardware Protection ............................................................................................ 99
7.5.2 Software Protection.............................................................................................. 99
7.5.3 Error Protection.................................................................................................... 99
7.6 Programmer Mode ............................................................................................................ 100
7.7 Power-Down States for Flash Memory............................................................................. 100
Section 8 RAM ..................................................................................................101
Section 9 I/O Ports .............................................................................................103
9.1 Port 1................................................................................................................................. 103
9.1.1 Port Mode Register 1 (PMR1) ............................................................................. 104
9.1.2 Port Control Register 1 (PCR1) ........................................................................... 105
9.1.3 Port Data Register 1 (PDR1)................................................................................ 105
9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................... 106
9.1.5 Pin Functions ....................................................................................................... 106
9.2 Port 2................................................................................................................................. 108
9.2.1 Port Control Register 2 (PCR2) ........................................................................... 109
9.2.2 Port Data Register 2 (PDR2)................................................................................ 109
9.2.3 Pin Functions ....................................................................................................... 109
9.3 Port 5................................................................................................................................. 111
9.3.1 Port Mode Register 5 (PMR5) ............................................................................. 112
Rev. 4.00, 03/04, page xi of xxviii
11 Page | ||
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