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PDF NTMSD2P102LR2 Data sheet ( Hoja de datos )
| Número de pieza | NTMSD2P102LR2 | |
| Descripción | Power MOSFET and Shottky Diode Dual SO-8 Package | |
| Fabricantes | ON Semiconductor | |
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NTMSD2P102LR2
FETKY™
Power MOSFET and Schottky Diode
Dual SO−8 Package
Features
• High Efficiency Components in a Single SO−8 Package
• High Density Power MOSFET with Low RDS(on),
Schottky Diode with Low VF
• Logic Level Gate Drive
• Independent Pin−Outs for MOSFET and Schottky Die
Allowing for Flexibility in Application Use
• Less Component Placement for Board Space Savings
• SO−8 Surface Mount Package,
Mounting Information for SO−8 Package Provided
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Thermal Resistance − Junction−to−Ambient
(Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 100°C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
VDSS
VGS
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
TJ, Tstg
−20
"10
V
V
175
0.71
−2.3
−1.45
−9.0
°C/W
W
A
A
A
105
1.19
−2.97
−1.88
−12
°C/W
W
A
A
A
62.5
2.0
−3.85
−2.43
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −20 Vdc, VGS = −4.5 Vdc, Peak IL
= −5.0 Apk, L = 28 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
TL
350 mJ
260 °C
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), Steady State.
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
MOSFET
−2.3 AMPERES
−20 VOLTS
90 mW @ VGS = −4.5 V
SCHOTTKY DIODE
2.0 AMPERES
20 VOLTS
580 mV @ IF = 2.0 A
8
1
SO−8
CASE 751
STYLE 18
A 18 C
A
27
C
S 3 6D
G 45 D
TOP VIEW
MARKING DIAGRAM
& PIN ASSIGNMENTS
Anode
Anode
Source
Gate
1
2
3
E2P102
LYWW
4
8 Cathode
7
Cathode
6
Drain
5
Drain
(Top View)
E2P102 = Device Code
L = Assembly Location
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTMSD2P102LR2 SO−8 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 1
1
Publication Order Number:
NTMSD2P102LR2/D
1 page  
NTMSD2P102LR2
1500
1200
Ciss
900
Crss
600
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
300
0
10
5 05
−VGS −VDS
Coss
Crss
10 15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
5 20
QT 18
4 16
14
3
Q1
2
Q2
VGS
12
10
8
1 VDS
ID = −2.4 A
TJ = 25°C
6
4
2
00
0 2 4 6 8 10 12 14
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
VDD = −10 V
ID = −1.2 A
VGS = −2.7 V
100 td (off)
tr tf
100
tr
td (off)
tf
10
1.0
td (on)
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
td
10 (on)
VDD = −10 V
ID = −2.4 A
VGS = −4.5 V
1.0
1.0
10
RG, GATE RESISTANCE (OHMS)
100
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
2
VGS = 0 V
1.6 TJ = 25°C
1.2
0.8
0.4
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
0
0.4 0.5 0.6 0.7 0.8 0.9
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
1
Figure 12. Diode Reverse Recovery Waveform
http://onsemi.com
5
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