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PDF 74C910 Data sheet ( Hoja de datos )
| Número de pieza | 74C910 | |
| Descripción | MM74C910 | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74C910 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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September 1989
MM54C910 MM74C910 256 Bit TRI-STATE
Random Access Read Write Memory
General Description
The MM54C910 MM74C910 is a 64 word by 4-bit random
access memory Inputs consist of six address lines four
data input lines a WE and a ME line The six address lines
are internally decoded to select one of the 64 word loca-
tions An internal address register latches the address infor-
mation on the positive to negative transition of ME The
TRI-STATE outputs allow for easy memory expansion
Address Operation Address inputs must be stable (tSA)
prior to the positive to negative transition of ME and (tHA)
after the positive to negative transition of ME The address
register holds the information and stable address inputs are
not needed at any other time
Write Operation Data is written into memory at the select-
ed address if WE goes low while ME is low WE must be
held low for tWE and data must remain stable tHD after WE
returns high
Read Operation Data is nondestructively read from a
memory location by an address operation with WE held
high
Outputs are in the TRI-STATE (Hi-Z) condition when the
device is writing or disabled
Features
Y Supply voltage range
Y High noise immunity
Y TTL compatible fan out
Y Input address register
Y Low power consumption
Y Fast access time
Y TRI-STATE outputs
Y High voltage inputs
3 0V to 5 5V
0 45VCC (typ )
1 TTL load
250 nW package (typ )
(chip enabled or disabled)
250 ns (typ ) at 5 0V
Logic Diagrams
www.DataSheet4U.com
Input Protection
u.comTRI-STATE is a registered trademark of National Semiconductor Corporation
www.datasheet4C1995 National Semiconductor Corporation TL F 5914
TL F 5914– 1
TL F 5914– 2
RRD-B30M105 Printed in U S A
1 page  
Switching Time Waveforms (Continued)
Read Modify Write Cycle
(See Note 1)
TL F 5914 – 10
t0H t1H
TL F 5914 – 11
Note 1 MEMORY ENABLE must be brought high for tME nanoseconds between every address change
Note 2 tr e tf e 20 ns for all inputs
Connection Diagram
Dual-In-Line Package
TL F 5914 – 12
Order Number MM54C910 or MM74C910
Top View
TL F 5914 – 3
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74C910.PDF ] | |
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