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PDF 74ALS540 Data sheet ( Hoja de datos )
| Número de pieza | 74ALS540 | |
| Descripción | SN74ALS540 | |
| Fabricantes | ETC | |
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SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025C – APRIL 1982 – REVISED JANUARY 1995
• 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
• pnp Inputs Reduce dc Loading
• Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal buffers and line drivers are designed
to have the performance of the popular
SN54ALS240A/ SN74ALS240A series and, at the
same time, offer a pinout with inputs and outputs
on opposite sides of the package. This
arrangement greatly facilitates printed-circuit-
board layout.
SN54ALS541 . . . J PACKAGE
SN74ALS540, SN74ALS541 . . . DW OR N PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
SN54ALS541 . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input NOR such that
if either output-enable (OE1 or OE2) input is high,
all eight outputs are in the high-impedance state.
The SN74ALS540 provides inverted data. The
′ALS541 provide true data at the outputs.
The -1 versions of SN74ALS540 and
SN74ALS541 are identical to the standard
versions, except that the recommended maximum
IOL is increased to 48 mA. There is no -1 version
of the SN54ALS541.
A3
3 2 1 20 19
4 18
Y1
A4 5
17 Y2
A5 6
16 Y3
A6 7
15 Y4
A7 8
14 Y5
9 10 11 12 13
The SN54ALS541 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74ALS540 and SN74ALS541 are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
1
1 page  
From Output
Under Test
CL
(see Note A)
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025C – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
VCC
Test
Point
RL
From Output
Under Test
CL
(see Note A)
RL
Test
Point
7V
RL = R1 = R2
S1
From Output
Under Test
CL
(see Note A)
R1
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
Data
Input
tsu
1.3 V
th
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
0.3 V
3.5 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
1.3 V
tw
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
tPZL
Waveform 1
S1 Closed
(see Note B)
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
1.3 V
tPHZ
1.3 V
1.3 V
tPLZ
3.5 V
0.3 V
[3.5 V
VOL
0.3 V
VOH
0.3 V
[0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ALS540.PDF ] | |
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