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PDF HN58X25256I Data sheet ( Hoja de datos )
| Número de pieza | HN58X25256I | |
| Descripción | (HN58X25128I / HN58X25256I) EEPROM | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HN58X25256I (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Pin Arrangement
HN58X25128I/HN58X25256I
8-pin SOP
S1
8
Q2
W3
7
6
VSS 4
5
(Top view)
VCC
HOLD
C
D
S
Q
NC
NC
NC
W
VSS
Pin Description
Pin name
C
D
Q
S
W
HOLD
VCC
V
SS
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
14-pin TSSOP
1 14
2 13
3 12
4 11
5 10
69
78
(Top view)
VCC
HOLD
NC
NC
NC
C
D
Rev.0.0, Nov. 2002, page 3 of 27
5 Page 
HN58X25128I/HN58X25256I
(Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V)
Parameter
Symbol Alt
Min Max
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not
active
f
C
t
SLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
t
CL
t
CLCH
tCHCL
tDVCH
tCHDX
tHHCH
f—
SCK
3
t
CSS1
100
—
tCSS2
100
—
tCS 150 —
tCSH 100 —
— 100 —
tCLH 150 —
t 150 —
CLL
t—
RC
1
tFC — 1
tDSU 30
—
tDH 50 —
— 140 —
Clock low hold time after HOLD active tHLCH — 90 —
Clock high setup time before HOLD tCHHL — 120 —
active
Clock high setup time before HOLD tCHHH — 120 —
not active
Output disable time
t
SHQZ
t—
DIS
200
Clock low to output valid
tCLQV
tV
— 120
Output hold time
tCLQX tHO 0
—
Output rise time
tQLQH tRO —
100
Output fall time
tQHQL tFO —
100
HOLD high to output low-Z
t t — 100
HHQX
LZ
HOLD low to output low-Z
t t — 100
HLQZ
HZ
Write time
tW
tWC —
8
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
2
2
2
2
2
2
2
Rev.0.0, Nov. 2002, page 9 of 27
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet HN58X25256I.PDF ] | |
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