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PDF HN58X2532I Data sheet ( Hoja de datos )

Número de pieza HN58X2532I
Descripción (HN58X2532I / HN58X2564I) EEPROM
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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No Preview Available ! HN58X2532I Hoja de datos, Descripción, Manual

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

1 page




HN58X2532I pdf
Pin Arrangement
HN58X2532I/HN58X2564I
8-pin SOP/TSSOP/SON
S1
Q2
8 VCC
7 HOLD
W3
6C
VSS 4
5D
Pin Description
Pin name
C
D
Q
S
W
HOLD
VCC
VSS
(Top view)
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
Rev.0.0, Mar. 2003, page 3 of 31

5 Page





HN58X2532I arduino
HN58X2532I/HN58X2564I
(Ta = 40 to +85°C, VCC = 1.8 V to 3.6 V)
Parameter
Symbol Alt
Min Max
Clock frequency
S active setup time
S not active setup time
S deselect time
S active hold time
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not
active
fC
t
SLCH
t
SHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
t
CLCH
t
CHCL
tDVCH
tCHDX
tHHCH
fSCK
3
t
CSS1
100
t
CSS2
100
tCS 150
tCSH 100
100
tCLH 150
tCLL 150
t
RC
1
t 1
FC
tDSU 30
tDH 50
140
Clock low hold time after HOLD active tHLCH 90
Clock high setup time before HOLD tCHHL 120
active
Clock high setup time before HOLD tCHHH 120
not active
Output disable time
t
SHQZ
t
DIS
200
Clock low to output valid
t
CLQV
t
V
120
Output hold time
tCLQX tHO 0
Output rise time
tQLQH tRO
100
Output fall time
tQHQL tFO
100
HOLD high to output low-Z
tHHQX
tLZ
100
HOLD low to output high-Z
t t 100
HLQZ
HZ
Write time
t t 8
W WC
Notes: 1. tCH + tCL 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes
1
1
2
2
2
2
2
2
2
Rev.0.0, Mar. 2003, page 9 of 31

11 Page







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