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PDF SCANSTA112 Data sheet ( Hoja de datos )
| Número de pieza | SCANSTA112 | |
| Descripción | 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2004
SCANSTA112
7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer
General Description
The SCANSTA112 extends the IEEE Std. 1149.1 test bus
into a multidrop test bus environment. The advantage of a
multidrop approach over a single serial scan chain is im-
proved test throughput and the ability to remove a board
from the system and retain test access to the remaining
modules. Each SCANSTA112 supports up to 7 local
IEEE1149.1 scan chains which can be accessed individually
or combined serially.
Addressing is accomplished by loading the instruction regis-
ter with a value matching that of the Slot inputs. Backplane
and inter-board testing can easily be accomplished by park-
ing the local TAP Controllers in one of the stable TAP Con-
troller states via a Park instruction. The 32-bit TCK counter
enables built in self test operations to be performed on one
port while other scan chains are simultaneously tested.
The STA112 has a unique feature in that the backplane port
and the LSP0 port are bidirectional. They can be configured
to alternatively act as the master or slave port so an alternate
test master can take control of the entire scan chain network
from the LSP0 port while the backplane port becomes a
slave.
Features
n True IEEE 1149.1 hierarchical and multidrop
addressable capability
n The 8 address inputs support up to 249 unique slot
addresses, an Interrogation Address, Broadcast
Address, and 4 Multi-cast Group Addresses (address
000000 is reserved)
n 7 IEEE 1149.1-compatible configurable local scan ports
n Bi-directional Backplane and LSP0 ports are
interchangeable slave ports
n Capable of ignoring TRST of the backplane port when it
becomes the slave.
n Stitcher Mode bypasses level 1 and 2 protocols
n Mode Register0 allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n Transparent Mode can be enabled with a single
instruction to conveniently buffer the backplane IEEE
1149.1 pins to those on a single local scan port
n General purpose local port passthrough bits are useful
for delivering write pulses for Flash programming or
monitoring device status.
n Known Power-up state
n TRST on all local scan ports
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can become TRI-STATE via the OE input to
allow an alternate test master to take control of the local
TAPs (LSP0-3 have a TRI-STATE notification output)
n 3.0-3.6V VCC Supply Operation
n Supports live insertion/withdrawal
20051250
FIGURE 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.
© 2004 National Semiconductor Corporation DS200512
www.national.com
1 page  
Connection Diagrams (Continued)
TQFP pinout
20051260
5 www.national.com
5 Page 
AC Electrical Characteristics: Scan Bridge Mode (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 5).
Symbol
Parameter
Conditions
Typ
tPHL,
tPLH
tPHL,
tPLH
tPHL
tPHL
tPZL,
tPZH
tPHL,
tPLH
Propagation Delay
TCKB0 to TRST(01-06)
Propagation Delay
TCKB1 to TRST(01-06)
Propagation Delay
TCKBn to TRISTBn
Propagation Delay
TCKBn to TRIST(01-03)
Propagation Delay
TCKBn to TDOBn or TDO(01-06)
Propagation Delay
An to Yn
12.0
12.0
8.5
8.0
9.0
6.0
Max
18.5
18.5
12.5
12.0
14.5
9.0
Units
ns
ns
ns
ns
ns
ns
AC Timing Characteristics: Scan Bridge Mode
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 4, 5).
Symbol
Parameter
Conditions
Min Max
tS
tH
tS
tH
tS
tH
tREC
tW
tWL
FMAX
Setup Time
TMSBn to TCKBn
Hold Time
TMSBn to TCKBn
Setup Time
TDIBn to TCKBn
Hold Time
TDIBn to TCKBn
Setup Time
TDI(01-06) to TCKBn
Hold Time
TDI(01-06) to TCKBn
Recovery Time
TCKBn from TRSTBn
Clock Pulse Width
TCKBn(H or L)
Reset Pulse Width
TRSTBn(L)
Maximum Clock Frequency (Note 6)
tR/tF = 1.0ns
tR/tF = 1.0ns
tR/tF = 1.0ns
2.5
1.5
3.0
2.0
1.0
3.5
1.0
10.0
2.5
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note 4: Guaranteed by Design (GBD) by statistical analysis
Note 5: RL = 500Ω to GND, CL = 50pF to GND, tR/tF = 2.5ns, Frequency = 25MHz, VM = 1.5V
Note 6: When sending vectors one-way to a target device on an LSP (such as in FPGA/PLD configuration/programming), the clock frequency may be increased
above this specification. In Scan Mode (expecting to capture returning data at the LSP), the FMAX must be limited to the above specification.
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| PDF Descargar | [ Datasheet SCANSTA112.PDF ] | |
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