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PDF SCANSTA111 Data sheet ( Hoja de datos )
| Número de pieza | SCANSTA111 | |
| Descripción | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 2004
SCANSTA111
Enhanced SCAN bridge
Multidrop Addressable IEEE 1149.1 (JTAG) Port
General Description
The SCANSTA111 extends the IEEE Std. 1149.1 test bus
into a multidrop test bus environment. The advantage of a
multidrop approach over a single serial scan chain is im-
proved test throughput and the ability to remove a board
from the system and retain test access to the remaining
modules. Each SCANSTA111 supports up to 3 local
IEEE1149.1 scan rings which can be accessed individually
or combined serially. Addressing is accomplished by loading
the instruction register with a value matching that of the Slot
inputs. Backplane and inter-board testing can easily be ac-
complished by parking the local TAP Controllers in one of the
stable TAP Controller states via a Park instruction. The 32-bit
TCK counter enables built in self test operations to be per-
formed on one port while other scan chains are simulta-
neously tested.
Features
n True IEEE 1149.1 hierarchical and multidrop
addressable capability
n The 7 slot inputs support up to 121 unique addresses,
an Interrogation Address, Broadcast Address, and 4
Multi-cast Group Addresses (address 000000 is
reserved)
n 3 IEEE 1149.1-compatible configurable local scan ports
n Mode Register0 allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n Transparent Mode can be enabled with a single
instruction to conveniently buffer the backplane IEEE
1149.1 pins to those on a single local scan port
n LSP ACTIVE outputs provide local port enable signals
for analog busses supporting IEEE 1149.4.
n General purpose local port passthrough bits are useful
for delivering write pulses for FPGA programming or
monitoring device status.
n Known Power-up state
n TRST on all local scan ports
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can become TRI-STATE via the OE input to
allow an alternate test master to take control of the local
TAPs (LSP0-2 have a TRI-STATE notification output)
n 3.0-3.6V VCC Supply Operation
n Power-off high impedance inputs and outputs
n Supports live insertion/withdrawal
Connection Diagrams
10124502
© 2004 National Semiconductor Corporation DS101245
10124516
www.national.com
1 page  
TABLE 2. Pin Descriptions (Continued)
No.
Pin Name
Pins I/O
Description
TRST(0-2)
3 O LOCAL TEST RESETS: A gated version of TRSTB (Note 2). These outputs have 24mA of
drive current.
A(0-1)
2 I LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the
backplane pin YB. (Only on LSP0 and LSP1. Only available when a single LSP is selected)
(Note 2). These inputs have an internal pull-up resistor.
Y(0-1)
2 O LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the
backplane pin AB. (Only on LSP0 and LSP1. Only available when a single LSP is selected)
(Note 2). These outputs have 24mA of drive current.
LSP_ACTIVE(0-2) 3 O LOCAL ANALOG TEST BUS ENABLE: These analog pins serve as enable signals for analog
busses supporting the IEEE 1149.4 Mixed-Signal Test Bus standard (Note 2), or for
backplane physical layer changes (i.e.; TTL to LVDS). These outputs have 12mA of drive
current.
TRIST(0-2)
3 O LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports
are TRI-STATEd (Note 2). These pins are used for backplane physical layer changes (i.e.;
TTL to LVDS). These outputs have 12mA of drive current.
GPIn
GPOn
TEST ENABLE
N/A I DEDICATED GENERAL PURPOSE INPUTS: These dedicated inputs (available in HDL) are
controlled by registers that can be read or written using the dot1 backplane pins (TDIB,
TDOB, TMSB and TCKB) (Note 3).
N/A O DEDICATED GENERAL PURPOSE OUTPUTS: These dedicated outputs (available in HDL)
are controlled by registers that can be read or written using the dot1 backplane pins (TDIB,
TDOB, TMSB and TCKB) (Note 3).
1 I TEST ENABLE INPUT: This pin is used for factory test and should be tied to VCC for normal
operation.
Note 1: The Silicon device will has seven (7) slot address pins. The HDL version is paramaterized to optionally allow 6, 7 or 8.
Note 2: The Silicon device will has three (3) LSP’s. The HDL version is paramaterized to optionally allow up to 8 total LSPs.
Note 3: Up to four (4) GPI/O’s per LSP. This feature is only available in the HDL version.
Note 4: Refer to the IBIS model on our website for I/O characteristics.
Application Overview
ADDRESSING SCHEME - The SCANSTA111 architecture
extends the functionality of the IEEE 1149.1 Standard by
supplementing that protocol with an addressing scheme
which allows a test controller to communicate with specific
’STA111s within a network of ’STA111s. That network can
include both multi-drop and hierarchical connectivity. In ef-
fect, the ’STA111 architecture allows a test controller to
dynamically select specific portions of such a network for
participation in scan operations. This allows a complex sys-
tem to be partitioned into smaller blocks for testing purposes.
The ’STA111 provides two levels of test-network partitioning
capability. First, a test controller can select individual
’STA111s, specific sets of ’STA111s (multi-cast groups), or all
’STA111s (broadcast). This ’STA111-selection process is
supported by a Level-1 communication protocol. Second,
within each selected ’STA111, a test controller can select
one or more of the chip’s three local scan-ports. That is,
individual local ports can be selected for inclusion in the
(single) scan-chain which a ’STA111 presents to the test
controller. This mechanism allows a controller to select spe-
cific terminal scan-chains within the overall scan network.
The port-selection process is supported by a Level-2 proto-
col.
HIERARCHICAL SUPPORT - Multiple SCANSTA111’s can
be used to assemble a hierarchical boundary-scan tree. In
such a configuration, the system tester can configure the
local ports of a set of ’STA111s so as to connect a specific
set of local scan-chains to the active scan chain. Using this
capability, the tester can selectively communicate with spe-
cific portions of a target system. The tester’s scan port is
connected to the backplane scan port of a root layer of
’STA111s, each of which can be selected using multi-drop
addressing. A second tier of ’STA111s can be connected to
this root layer, by connecting a local port (LSP) of a root-
layer ’STA111 to the backplane port of a second-tier
’STA111. This process can be continued to construct a multi-
level scan hierarchy. ’STA111 local ports which are not cas-
caded into higher-level ’STA111s can be thought of as the
terminal leaves of a scan tree. The test master can select
one or more target leaves by selecting and configuring the
local ports of an appropriate set of ’STA111s in the test tree.
Check with your ATPG tool vendor to ensure support of this
feature.
State Machines
The ’STA111 is IEEE 1149.1-compatible, in that it supports
all required 1149.1 operations. In addition, it supports a
higher level of protocol, (Level 1), that extends the IEEE
1149.1 Std. to a multi-drop environment.
In multi-drop scan systems, a scan tester can select indi-
vidual ’STA111s for participation in upcoming scan opera-
tions. STA111 selection is accomplished by simultaneously
scanning a device address out to multiple STA111s. Through
an on-chip address matching process, only those ’STA111s
whose statically-assigned address matches the scanned-out
5 www.national.com
5 Page 
Level 1 Protocol (Addressing Modes) (Continued)
FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register
10124510
FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register
10124511
Level 2 Protocol
Once the SCANSTA111 has been successfully addressed
and selected, its internal registers may be accessed via
Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std.
1149.1 TAP protocol with one exception: if the ’STA111 is
selected via the Broadcast or Multi-Cast address, TDOB is
always TRI-STATED. (The TDOB buffer must be imple-
mented this way to prevent bus contention.) Upon being
selected, (i.e., the ’STA111 Selection controller transitions
from the Wait-For-Address state to one of the Selected
states), each of the local scan ports (LSP0 , LSP1 , LSP2)
remains parked in one of the following four TAP Controller
states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, or
11 www.national.com
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| PDF Descargar | [ Datasheet SCANSTA111.PDF ] | |
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