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SCANSTA101 PDF даташит

Спецификация SCANSTA101 изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Low Voltage IEEE 1149.1 STA Master».

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Номер произв SCANSTA101
Описание Low Voltage IEEE 1149.1 STA Master
Производители National Semiconductor
логотип National Semiconductor логотип 

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SCANSTA101 Даташит, Описание, Даташиты
October 2002
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor
overhead while remaining flexible. The device architecture
supports IEEE 1149.1, BIST, and IEEE 1532. The flexibility
will allow it to adapt to any changes that may occur in 1532
and support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and
reduces the software overhead that is associated with ap-
plying serial patterns with a parallel processor. The SCAN-
STA101 features a generic Parallel Processor Interface
(PPI) which operates by serializing data from the parallel bus
for shifting through the chain of 1149.1 compliant compo-
nents (i.e., scan chain). Writes can be controlled either by
wait states or the DTACK line. Handshaking is accomplished
with either polling or interrupts.
Features
n Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software Rev 2.0
n Available as a Silicon Device and Intellectual Property
(IP) model for embedding into VLSI devices
n Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n 16-bit Data Interface (IP scalable to 32-bit)
n 2Kx32 bit dual-port memory addressing for access by
the PPI or the 1149.1 master
n Load-on-the-fly (LotF) and Preload operating modes
supported
n On-Board Sequencer allows multi-vector operations
such as those required to load data into an FPGA
n On-Board Compares support TDI validation against
preloaded expected data
n 32-bit Linear Feedback Shift Register (LFSR) at the Test
Data In (TDI) port
n State, Shift, and BIST macros allow predetermined TMS
sequences to be utilized
n Operates at 3.3v supply voltages w/ 5V tolerant I/O
n Outputs support Power-Down TRI-STATE mode.
SCANSTA101 Architecture
FIGURE 1.
© 2002 National Semiconductor Corporation DS101215
10121502
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SCANSTA101 Даташит, Описание, Даташиты
SCANSTA101 Architecture (Continued)
Figure 1 shows a high level view of the SCANSTA101 Scan
Master and its interface groups. Table 1 provides a brief
description of each of these interface groups. Table 2 pro-
vides a brief description of the external interfaces. The de-
vice is composed of three interfaces around a dual-port
memory. These interfaces consist of the Parallel Processor
Interface (PPI), Serial Scan Interface (SSI), and Test and
Debug Interface. The System Input block is included only to
designate inputs that have global use across the device. The
Test and Debug interface supports BIST, boundary scan,
and internal scan for this device.
TABLE 1. Interface Descriptions
Interface
Parallel Processor Interface
Serial Scan Interface
Test and Debug Interface
System Inputs
Description
Used for configuration, ScanMaster scan chain loads and reads, programmable device
file loads and reads, and status monitoring.
Performs parallel to serial conversion, sequences and formats the outgoing serial
stream to conform to 1149.1 protocol.
Interfaces used for manufacturing tests, this includes a JTAG interface and a scan
interface. The three scan interface pins are shared with three of the data pins.
Interface inputs for system control, i.e. clock, reset and output tristate control.
Connection Diagrams
10121503
SSOP Package Pinout
(Top View)
BGA Package Pinout
(Top View)
10121540
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SCANSTA101 Даташит, Описание, Даташиты
TABLE 2. Pin Descriptions
Pin
Name
VCC
GND
D(15:0)
D(31:16)
(Note 1)
A(4:0)
SCK
INT
OE
DTACK
R/W
STB
CE
RST
TDO
TDI
TMS
TCK
TRST
TDI_SM
TDO_SM
TMS_SM
TCK_SM
TRST0_SM
TRST1_SM
(Note 1)
TRIST_SM
No.
Pins
4
4
16
16
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
I/O
N/A Power
N/A Ground
I/O Bidirectional Data Bus. Signals are bonded out for the packaged device.
D15 and D14 are shared pins with SCAN_IN, and SCAN_OUT
respectively.
I/O Bidirectional Data Bus. These signals are not available in the packaged
device.
I Address Bus
I The system clock that drives all internal timing. TCK_SM is a gated,
divided and buffered version of SCK.
O Interrupt Output
I Output enable that tristates all 1149.1 "_SM" outputs when high.
O DTACK is used to synchronize asynchronous transfers between the host
and the STA101. When CE is high, DTACK is tristated. When CE is low,
DTACK is enabled. DTACK goes low when data has been registered and
then goes tri-state when the cycle has completed.
I R/W defines a PPI cycle. Read when high, write when low.
I Strobe is used for timing all PPI transfers. D(15:0), or D(31:0) in 32-bit
mode, are tristated when STB is high. Data valid setup is with respect to
the falling edge of STB and data valid hold is with respect to rising edge of
STB.
I Chip Enable, when low, enables the PPI for data transfers. CE can remain
low during back-to-back accesses. D(15:0), or D(31:0) in 32-bit mode, and
DTACK are tristated when CE is high.
I Asynchronous reset, when low, initializes the STA101.
O Test Data Out is the serial scan output from the STA101. TDO is enabled
when OE is low.
I Test Data In is the serial scan input to the STA101.
I Test Mode Select. The Test Mode Select pin is a serial input used to
accept control logic to the Test & debug interface.
I Test Clock Input for 1149.1
I Test Reset
I Scan Master Test Data Input in the Serial Scan Interface
O Scan Master Test Data Output in the Serial Scan Interface
O Scan Master Test Mode Select in the Serial Scan Interface
O Scan Master Test Clock in the Serial Scan Interface
O Scan Master Test Reset output in the Serial Scan Interface
O Redundent ScanMaster TRST. This signal is not available for the
packaged device.
O The TRI-STATE notification pin exerts a high signal when TDO_SM is
TRI-STATED
Note 1: D(31:16) in the Parallel Processor Interface and TRST1_SM in the Serial Scan Interface are not bonded out for the packaged part. These are used in the
32-bit Macro Mode only.
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Номер в каталогеОписаниеПроизводители
SCANSTA101SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master (Rev. J)Texas Instruments
Texas Instruments
SCANSTA101Low Voltage IEEE 1149.1 STA MasterNational Semiconductor
National Semiconductor

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