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PDF NHPXA270 Data sheet ( Hoja de datos )
| Número de pieza | NHPXA270 | |
| Descripción | Microprocessor | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel® PXA270 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
■ High-performance processor:
— Intel XScale® microarchitecture with
Intel® Wireless MMX™ Technology
— 7 Stage pipeline
— 32 KB instruction cache
— 32 KB data cache
— 2 KB “mini” data cache
— Extensive data buffering
■ 256 Kbytes of internal SRAM for high
speed code or data storage preserved
during low-power states
■ High-speed baseband processor interface
(Mobile Scalable Link)
■ Rich serial peripheral set:
— AC’97 audio port
— I2S audio port
— USB Client controller
— USB Host controller
— USB On-The-Go controller
— Three high-speed UARTs (two with
hardware flow control)
— FIR and SIR infrared communications
port
■ Hardware debug features — IEEE JTAG
interface with boundary scan
■ Hardware performance-monitoring
features with on-chip trace buffer
■ Real-time clock
w ■ Operating-system timers
w ■ LCD Controller
w ■ Universal Subscriber Identity Module
.DataSheet4U.cominterface
■ Low power:
— Wireless Intel Speedstep® Technology
— Less than 500 mW typical internal
dissipation
— Supply voltage may be reduced to
0.85 V
— Four low-power modes
— Dynamic voltage and frequency
management
■ High-performance memory controller:
— Four banks of SDRAM: up to 104 MHz
@ 2.5V, 3.0V, and 3.3V I/O interface
— Six static chip selects
— Support for PCMCIA and Compact
Flash
— Companion chip interface
■ Flexible clocking:
— CPU clock from 104 to 624 MHz
— Flexible memory clock ratios
— Frequency changes
— Functional clock gating
■ Additional peripherals for system
connectivity:
— SD Card / MMC Controller (with SPI
mode support)
— Memory Stick card controller
— Three SSP controllers
— Two I2C controllers
— Four pulse-width modulators (PWMs)
— Keypad interface with both direct and
matrix keys support
— Most peripheral pins double as GPIOs
Order Number 280002-005
1 page  
Intel® PXA270 Processor
Contents
Tables
6-12 32-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21
6-13 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22
6-14 16-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23
6-15 Synchronous Flash Burst-of-Eight Read Timing ..............................................6-26
6-16 Synchronous Flash Stacked Burst-of-Eight Read Timing ................................6-27
6-17 First-Access Latency Configuration Timing......................................................6-28
6-18 Synchronous Flash Burst Read Example.........................................................6-30
6-19 32-Bit Flash Write Timing .................................................................................6-31
6-20 32-Bit Stacked Flash Write Timing ...................................................................6-32
6-21 16-Bit Flash Write Timing .................................................................................6-33
6-22 32-Bit SRAM Write Timing ...............................................................................6-35
6-23 16-bit SRAM Write for 4/2/1 Byte(s) Timing .....................................................6-36
6-24 32-Bit VLIO Read Timing .................................................................................6-38
6-25 32-Bit VLIO Write Timing..................................................................................6-39
6-26 Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41
6-27 Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42
6-28 LCD Timing Definitions.....................................................................................6-43
6-29 SSP Master Mode Timing Definitions...............................................................6-44
6-30 Timing Diagram for SSP Slave Mode Transmitting Data to an External
Peripheral .........................................................................................................6-44
6-31 Timing Diagram for SSP Slave Mode Receiving Data from External
Peripheral .........................................................................................................6-45
6-32 JTAG Boundary-Scan Timing...........................................................................6-46
1-1 Supplemental Documentation ............................................................................1-2
3-1 Processor Material Properties ............................................................................3-7
4-1 Pin Use Summary ............................................................................................4-10
4-2 Pin Use and Mapping Notes.............................................................................4-27
4-3 Signal Types.....................................................................................................4-28
4-4 Memory Controller Pin Reset Values ...............................................................4-28
4-5 Discrete (13x13 VF-BGA) Power Supply Pin Summary...................................4-29
5-1 Absolute Maximum Ratings................................................................................5-1
5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2
5-3 Memory Voltage and Frequency Electrical Specifications .................................5-4
5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4
5-5 Internally Generated Power Domain Descriptions .............................................5-6
5-6 Core Voltage Specifications For Lower Power Modes .......................................5-6
5-7 Power-Consumption Specifications....................................................................5-7
5-8 Standard Input, Output, and I/O Pin DC Operating Conditions ..........................5-8
5-9 Typical 32.768-kHz Crystal Requirements .........................................................5-9
5-10 Typical External 32.768-kHz Oscillator Requirements ....................................5-11
5-11 Typical 13.000-MHz Crystal Requirements......................................................5-11
5-12 Typical External 13.000-MHz Oscillator Requirements....................................5-12
5-13 CLK_PIO Specifications ...................................................................................5-12
5-14 CLK_TOUT Specifications ...............................................................................5-12
5-15 48 MHz Output Specifications ..........................................................................5-13
6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1
6-2 Power-On Timing Specifications(OSCC[CRI] = 0) .............................................6-3
6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) ..................................6-4
Electrical, Mechanical, and Thermal Specification
v
5 Page 
Introduction
1
The Intel® PXA270 processor (PXA270 processor) provides industry-leading multimedia
performance, low-power capabilities, rich peripheral integration and second generation memory
stacking. Designed from the ground up for wireless clients, it incorporates the latest Intel advances
in mobile technology over its predecessor, the Intel® PXA255 processor. These same attributes
and features also make the PXA270 processor ideal for embedded applications. The PXA270
processor redefines scalability by operating from 104 MHz up to 624 MHz, providing enough
performance for the most demanding mobile applications.
The PXA270 processor is the first Intel processor to include Intel® Wireless MMX™ technology,
enabling high-performance, low-power multimedia acceleration with a general-purpose instruction
set. Intel® Quick Capture technology provides a flexible and powerful camera interface for
capturing digital images and video. While performance is key in the PXA270 processor, power
consumption is also a critical component. The new capabilities of Wireless Intel SpeedStep®
technology set the standard for low-power consumption.
The PXA270 processor is offered in two packages: 13x13 mm VFBGA and 23x23 mm PBGA.
1.1
1.1.1
1.1.2
About This Document
This document constitutes the electrical, mechanical, and thermal specifications for the PXA270
processor. It contains a functional overview, mechanical data, package signal locations, targeted
electrical specifications, and functional bus waveforms. For detailed functional descriptions other
than parametric performance, refer to the Intel® PXA27x Processor Family Developers Manual.
Number Representation
All numbers in this document are base 10 unless designated otherwise. Hexadecimal numbers have
a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is represented as 0x6B in
hexadecimal and 0b110_1011 in binary.
Typographical Conventions
All signal and register-bit names appear in uppercase. Active low items are prefixed with a
lowercase “n”.
Bits within a signal name are enclosed in angle brackets:
EXTERNAL_ADDRESS<31:0>
nCS<1>
Bits within a register bit field are enclosed in square brackets:
REGISTER_BITFIELD[3:0]
REGISTER_BIT[0]
Electrical, Mechanical, and Thermal Specification
1-1
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