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PDF HIP5060 Data sheet ( Hoja de datos )
| Número de pieza | HIP5060 | |
| Descripción | Power Control IC Single Chip PowerSupply | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HIP5060
®
Power Control IC Single Chip
PowerSupply
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File Number
• Single Chip Current Mode Control IC
3207.2
The HIP5060 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC. Both
the standard “Boost” and the “SEPIC” (Single-Ended
Primary Inductance Converter) power supply topologies are
easily implemented with this single control IC.
• 60V, 10A On-Chip DMOS Transistor
• Thermal Protection
• Over-Voltage Protection
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
• On-Chip Reference Voltage - 5.1V
Special power transistor current sensing circuitry is
incorporated that minimizes losses due to the monitoring
• Output Rise and Fall Times ~ 3ns
• Designed for 27V to 45V Operation
circuitry. Moreover, over-temperature and over-voltage
detection circuitry is incorporated within the IC to monitor the
Applications
chip temperature and the actual power supply output
• Single Chip Power Supplies
voltage. These circuits can disable the drive to the power
• Current Mode PWM Applications
transistor to protect both the transistor and, most
• Distributed Power Supplies
importantly, the load from over-voltage.
• Multiple Output Converters
As a result of the power DMOS transistor’s current and
voltage capability (10A and 60V), power supplies with output
power capability up to 100 watts are possible.
Ordering Information
PART NUMBER
HIP5060DY
HIP5060DW
TEMPERATURE
RANGE
0oC to +85oC
0oC to +85oC
PACKAGE
37 Pad Chip
Wafer
Chip
FLTH (37)
VREG (36)
VCMP (35)
PSOK (34)
SHRT (33)
PSEN (32)
TMON (31)
(8) VDDA
(9) V+
(10) SLCT
(11) CKIO
(12) DGD1
(13) VDDP
(14) VDDP
NOTE: Unused pads are for trim and test.
153 mils x 165 mils (3.88mm x 4.19mm)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
HIP5060
Pin Descriptions
PAD NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13 & 14
15, 16, 19, 20,
23, 24, 27, 28
17, 18, 21, 22,
25, 26, 29, 30
31
32
33
34
35
36
37
DESIGNATION
AGND
VINP
SFST
IRFO
IRFI
DGD2
VDDD
VDDA
V+
SLCT
CKIO
DGD1
VDDP
S
DESCRIPTION
Analog ground.
Internal 5.1V reference.
Controls the rate of rise of the output voltage. Time is determined by an internal 0.7µA current
source and an external capacitor.
A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current
sense comparator. The maximum current is set by the value of the resistor, according to the
equation: IPEAK = 32/R. Where R is the value of the external resistor in KΩ and must be greater
than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will
be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A.
See IRFO
Ground of the DMOS gate driver. This pad is used for bypassing.
Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.
This is the analog supply and internal 12V regulator output.
This is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.7µF capacitor and may be composed of seven,
single 0.1µF chip capacitors.
This pad provides for the option of using either internal 1MHz operation of for an external clock.
Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this termi-
nal to VDDD or 12V will allow application of an external clock to the IC via the CKIO pad. There
is an internal 50K pull down
Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to
12V.
This pad is the return for the digital supply.
These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS
source pads.
Source pads of the DMOS power transistor.
D Drain pads of the DMOS power transistor.
TMON
PSEN
SHRT
PSOK
VCMP
VREG
FLTN
This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into
the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a
nominal junction temperature of +125oC.
This terminal is provided to activate the converter. This terminal may be left open or returned to
5V for normal operation. When the input is low, the DMOS driver is disabled.
25µA is internally applied to this node when there is an over-current condition.
This pad provides a delayed positive indication when the supply is enabled.
Output of the transconductance amplifier. This node is used for both gain and frequency com-
pensation of the loop.
Input to the transconductance error amplifier is available on this pad. The other input is internally
connected to the 5.1V reference, VINP, Pad 2.
This is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when over-
temperature, over-voltage or over-current is experienced.
5
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