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Número de pieza | CA91 | |
Descripción | CMOS AccelArray | |
Fabricantes | Fujitsu Media Devices | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CA91 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! FUJITSU SEMICONDUCTOR
DATA SHEET
Semicustom
CMOS
AccelArrayTM
CA91 Series
DS06-10801-4E
■ DESCRIPTION
AccelArrayTM* is a new structured ASIC family, offering short development time, and low development cost with
pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.
By using 0.11 µm CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM
and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins)
packages are available.
* : AccelArrayTM is a trademark of Fujitsu Limited.
■ FEATURES
• High-speed, large scale ASIC produced in short development time:
TAT = One third compared with Standard Cell ASICs (target value)
• Uses an architecture that simplifies physical design tasks.
• Pre-designed common masters with IR-drop free.
• Pre-designed test circuit insertion to reduce test synthesis tasks.
• Uses a dedicated timing-driven layout tool to reduce development time.
• Signal Integrity Free (pre-designed main clock trees without design verifications)
• Max built-in gate number : 6,000,000 gates or more
• Technology : 0.11 µm Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
• Internal cells support high-speed operation
• Power supply voltage : +1.2 V ± 0.1 V/2.5 V ± 0.2 V (Dual power supply. Needs 1.5 V power supply during using
HTSL.) .
• Operation junction temperature : −40 °C to +125 °C (standard)
• Max operating frequency: 333 MHz (internal circuit)
• Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
• Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
• Embedded macro : PLL, SRAM
• 8-channel clock supply system incorporating a PLL
• Supports Memory-BIST/Boundary-SCAN
• Package : FC-BGA (729 pins to 1681 pins)
• ARM core is supported.
Note : It contains under planning.
1 page CA91 Series
■ ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
(VDDI = 1.2 V ± 0.1 V, VDDE = 2.5 V ± 0.2 V, VSS = 0 V, Tj = − 40 °C to + 125 °C)
Parameter
Symbol
Conditions
Value
Min Typ
Unit
Max
“H” level output voltage VOH IOH = − 100 µA
VDDE − 0.2 ⎯ VDDE V
“L” level output voltage VOL IOL = 100 µA
0 ⎯ 0.2 V
Input leak current *
IL
⎯
− 10
⎯ + 10 µA
Pull-up/Pull-down
resistor
2.5 V CMOS pin,
VIL = 0 V at pull-up,
RP VIH = VDDE at pull-down
3.3 V Tolerant pin,
VIH = 3.0 V to 3.6 V at pull-down
10 25 55 kΩ
12 33 85 kΩ
* : The input leak current may exceed the above value if an input buffer with pull-up or pull-down resistor is used.
Note : Refer to the application note for details of HSTL I/O.
2. AC CHARACTERISTICS
Parameter
Symbol
Delay time
tpd *1
Min
typ *2 × tmin *3
Value
Typ
typ *2 × ttyp *3
Max
typ *2 × tmax *3
*1 : Delay time = propagation delay time, enable time, and disable time.
*2 : typ can be estimated from the cell specification.
*3 : Measurement condition
Measurement condition
tmin
VDD = 1.2 V ± 0.1 V, VSS = 0 V, Tj = − 40 °C to + 125 °C
0.73
ttyp
1.00
Note : Obtains the tpd max corresponding to the maximum junction temperature Tj.
Unit
ns
tmax
1.43
■ I/O PIN CAPACITANCE
Parameter
Input pin
Output pin
I/O pin
Symbol
CIN
COUT
CI/O
(Tj = +25 °C, VDDE = VI = 0 V, f = 1 MHz)
Value
Unit
Max 16
pF
Max 16
pF
Max 16
pF
Note : The capacity depends on the package, pin positions, and similar.
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet CA91.PDF ] |
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