PDF IA4320 Data sheet ( Hoja de datos )

Número de pieza	IA4320
Descripción	Universal ISM Band FSK Transceiver
Fabricantes	Interation
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No Preview Available ! IFAS4K3R2t0eacSUehnievieevte4r rUs.acol mISM Band W I R E L E S SIA4D3A2T0A S H E E TDESCRIPTION .DaIntegration’s IA4320 is a single chip, low power, multi-channel FSK receiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the w315, 433, 868, and 915 MHz bands. Used in conjunction with IA4220/21, Integration wAssociates’ FSK transmitters, the IA4320 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are wintegrated. Only an external crystal and bypass filtering are needed for operation. mThe IA4320 has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency hopping, bypassing multipath fading, and ointerference to achieve robust wireless links. The PLL’s high resolution allows .cthe usage of multiple channels in any of the bands. The baseband bandwidth (BW) is programmable to accommodate various deviation, data rate, and crystal tolerance requirements. The receiver employs the Zero-IF approach with I/Q demodulation, therefore no external components (except crystal and decoupling) are needed in a Utypical application. The IA4320 is a complete analog RF and baseband receiver including a multi-band PLL synthesizer with an LNA, I/Q down converter mixers, t4baseband filters and amplifiers, and I/Q demodulator. The chip dramatically reduces the load on the microcontroller with integrated edigital data processing: data filtering, clock recovery, data pattern recognition and integrated FIFO. The automatic frequency control (AFC) feature allows using ea low accuracy (low cost) crystal. To minimize the system cost, the chip can provide a clock signal for the microcontroller, avoiding the need for two crystals. hFor simple applications, the receiver supports a standalone operation mode. This allows complete data receiver operation and control of four digital outputs based Son the incoming data pattern without a microcontroller. In this mode, 12 or more tapredefined frequency channels can be used in any of the four bands. For low power applications, the device supports low duty-cycle operation based on the internal wake-up timer. aBLOCK DIAGRAM .DIN1 13 wIN2 12 LNA MIX I AMP OC MIX Q Self cal. AMP OC ww omRFParts PLL & I/Q VCO with cal. RSSI BB Amp/Filt./Limiter I/Q Demod. Data Filt CLK Rec clk data DCLK/ CFIL/ 7 FFIT/ OUT2 DATA/ 6 nFFS/ OUT2 FIFO COMP DQD AFC Data processing units U.cCLK div et48 eCLK/ taShLPDM Xosc 9 XTL WTM with cal. LBD Low Power parts Controller Bias 15 1 2 34 5 16 10 ARSSI/ SDI/ SCK/ nSEL/ FFIT/ nIRQ/ VDI/ nRES/ FCS2 FCS0 FBS0 FBS1 SDO/ OUT1 FCS3 FCS1 OUT0 11 14 VSS VDD PIN ASSIGNMENT FCS0 FBS0 FBS1 OUT0 OUT1 OUT2 OUT3 LPDM FCS3 FCS2 VDD IN1 IN2 VSS FCS1 XTL SDI SCK nSEL FFIT/SDO nIRQ DATA/nFFS DCLK/CFIL/FFIT CLK VDI ARSSI VDD IN1 IN2 VSS nRES XTL Standalone Mode Microcontroller Mode See back page for ordering information. FEATURES • Fully integrated (low BOM, easy design-in) • No alignment required in production • Fast settling, programmable, high-resolution PLL • Fast frequency hopping capability • High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) • Direct differential antenna input • Programmable baseband bandwidth (67 to 400 kHz) • Analog and digital RSSI outputs • Automatic frequency control (AFC) • Data quality detection (DQD) • Internal data filtering and clock recovery • RX pattern recognition • SPI compatible serial control interface • Clock and reset signals for microcontroller • 16 bit RX data FIFO • Standalone operation mode without microcontroller • Low power duty-cycle mode (less than 0.5 mA average supply current) • Standard 10 MHz crystal reference • Alternative OOK support • Wake-up timer • Low battery detector • 2.2 to 5.4 V supply voltage • Low power consumption (~9 mA in low bands) • Low standby current (0.3 µA) • Compact 16-pin TSSOP package TYPICAL APPLICATIONS • Remote control • Home security and alarm • Wireless keyboard/mouse and other PC peripherals • Toy control • Remote keyless entry • Tire pressure monitoring • Telemetry • Personal/patient data logging • Remote automatic meter reading www.DaIA4320-DS Rev 1.29r 1005 PRELIMINARY 1 www.integration.com 1 page IA4320 PACKAGEPINDEFINITIONS,STANDALONEMODE Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output FCS0 FBS0 FBS1 OUT0 OUT1 OUT2 OUT3 LPDM 1 16 2 15 3 14 4 13 IA4320 5 12 6 11 7 10 89 FCS3 FCS2 VDD IN1 IN2 VSS FSC1 XTL Pin Name Type Function 1 FCS0 DI Frequency select input bit0 2 FBS0 DI Band select input bit0 3 FBS1 DI Band select input bit1 4 OUT0 DO Control output bit0 5 OUT1 DO Control output bit1 6 OUT2 DO Control output bit2 7 OUT3 DO Control output bit3 8 LPDM DI Low power duty cycle mode select input 9 XTL AIO Crystal connection (other terminal of crystal to VSS) or external reference input 10 FCS1 DI Frequency select input bit1 11 VSS S Negative supply voltage 12 IN2 AI RF differential signal input 13 IN1 AI RF differential signal input 14 VDD S Positive supply voltage 15 FCS2 DI Frequency select input bit2 16 FCS3 DI Frequency select input bit3 Typical Application, Standalone Mode VCC C1 C2 C3 1u 100p 10p GND To LED, SSR, etc. load: 3mA max. OUT0 OUT1 OUT2 OUT3 1 2 3 4 5 6 7 #8 IA4320 16 15 * 14 13 12 11 10 * 9 X1 10MHz Antenna 250 Ohm * Configuration pins: leave open or connect to VCC or GND # Configuration pin: connect to VCC or GND 5 5 Page IA4320 Frequency Setting Command Bbiitt 15 14 13 12 11 10 9 8 1 0 1 0 f11 f10 f9 f8 TThhee 1122--bbiitt FFrreeqquueennccyy SSeettttiinngg CCoommmmaanndd (<f1f111to: ff00)> hhaass tthhee vvaalulueeF.FT.hTehvealuvaeluFeshFouslhdobueldinbteheinratnhgee roafng9e6oaf n9d6 a3n9d0339.0W3.hWenheFn Fis isouotutooff rraannggee,, ththee pprreevvioiouuss vvaaluluee iiss kkeepptt.. TThhee ssyynntthheessizizeerr cceennteterr fffrr0eeq=quu1eefn00ncc=yMy1fHf000zcMcaanHnzCbeb1ecCac1lac(Cluc(2luaClt2+aetd+eFda/Fs4/a:40s00:000)) 76543210 f7 f6 f5 f4 f3 f2 f1 f0 ThTehecocnosntastnatsntsC1C1anadndCC22aarereddeetetermrminineedd bybtyhethseesleecletecdtebdanbdanads:as: Band [MHz] 315 433 868 915 C1 1 1 2 3 C2 31 43 43 30 Receiver Setting Command bit 15 14 13 12 11 10 110000 9 0 876543210 0 d1 d0 g1 g0 r2 r1 r0 eenr POR A680h POR C0C1h BBiittss 77--66 sseelleecctt tthhee VVDDII(v(vaalildidddaatataininddicicaatotor)r)sisginganla: l: d1 d0 00 00 00 11 11 00 11 11 VDDI outtpuutt DDiiggiittaall RRSSSSII OOuutt ((DDRRSSSSII)) DDatta QQualitty DDetteccttorr OOuttpputt ((DDQQDD)) Clloocckk rreccovverryy locckk DRSSAIlw&a&ys DQD BBiittss 55--44 LLNNAAggaaininsseet:t: g1 g0 00 01 10 11 BBiittss 33--11 ccoonnttrrooll tthhee tthhrreesshhoollddoofftthheeRRSSSSI Iddeetetectcotro:r: r2 r1 00 00 01 01 10 10 11 10 GLNA (dB relative to max. G) 0 -14 -6 -20 r0 RSSIsetth [dBm] 0 -103 1 -97 0 -91 1 -85 0 -79 1 -73 0 -67 1 -61 The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSIth = RSSIsetth + GLNA Bit 0 (en) enables the whole receiver chain and crystal ocsillator when set. Enable/disable of the wake-up timer and the low battery detector are not affected by this setting. Note: Clock tail is not generated when the crystal oscillator is controlled by en bit. 11 11 Page

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