NCP5355 PDF даташит
Спецификация NCP5355 изготовлена «ON Semiconductor» и имеет функцию, называемую «12V Synchronous Buck Power MOSFET Driver». |
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Детали детали
Номер произв | NCP5355 |
Описание | 12V Synchronous Buck Power MOSFET Driver |
Производители | ON Semiconductor |
логотип |
10 Pages
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N1P2oCwPV5eS3rSy5Mnh5eOcehSt4rFoUEn.cTooumDsriBveurckThe NCP5355 is a dual MOSFET gate driver optimized to drive the
tagates of both high− and low−side Power MOSFETs in a Synchronous
Buck converter. The NCP5355 is an excellent companion to
amultiphase controllers that do not have integrated gate drivers, such as
.DON Semiconductor’s NCP5314 or NCP5316. This architecture
wprovides the power supply designer greater flexibility by being able to
wlocate the gate drivers close to the MOSFETs.
w Driving MOSFETs with a 12 V source as opposed to a 5.0 V can
significantly reduce conduction losses. Optimized internal, adaptive
mnonoverlap circuitry further reduces switching losses by preventing
osimultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
.cvoltages as high as 26 V. Both gate outputs can be driven low by
applying a low logic level to the Enable (EN) pin. An Undervoltage
Lockout function ensures that both driver outputs are low when the
Usupply voltage is low, and a Thermal Shutdown function provides the
t4IC with overtemperature protection.
The NCP5355 has the same pinout as the NCP5351 5.0 V
Gate Driver.
eFeatures
e• 8.0 V − 14 V Gate Drive Capability
h• 2.0 A Peak Drive Current
• Rise and Fall Times < 15 ns Typical into 3300 pF
S• Propagation Delay from Inputs to Outputs < 30 ns
ta• Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
• Floating Top Driver Accommodates Applications Up to 26 V
a• Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
.D• Thermal Shutdown Protection Against Overtemperature
• TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn−On of Top MOSFET
w• BG to PGND Pulldown Resistor Prevents Transient Turn On of
Bottom MOSFET
w• Internal Bootstrap Diode Reduces Parts Count and Total
mSolution Cost
w heet4U.co• Pb−Free Package is Available
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MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
8
5355
ALYW
1
8
1
SOIC−8 EP
D SUFFIX
CASE 751AC
8
5355
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
PIN CONNECTIONS
1
DRN
TG
BST
CO
8
PGND
BG
VS
EN
ORDERING INFORMATION
Device
Package
Shipping†
NCP5355D
SOIC−8
98 Units/Rail
NCP5355DR2
SOIC−8 2500 / Tape & Reel
NCP5355DR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCP5355PDR2 SOIC−8 EP 2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.DataS© Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
December, 2004 − Rev. 7
NCP5355/D
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NCP5355
VS
PGND
CO
EN
5 V Regulator
5V
5V
Overtemp.
Shutdown
5 V VS
5V
−
+ UVLO
8.0/7.0 V
5V
5V
5V
2.0 mA
5V
5V
BST
5V
Level Shift
Nonoverlap
30 ns
5V
5V
Nonoverlap
30 ns
5 V VS
Level Shift
Driver
TG
100 k
DRN
30 k
20 k
20 k
30 k
VS
Driver
BG
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin Pin Symbol
Description
1
DRN
The switching node common to the high and low−side FETs. The high−side (TG) driver and supply (BST)
are referenced to this pin.
2 TG Driver output to the high−side MOSFET gate.
3 BST Bootstrap supply voltage input. In conjunction with an internal diode to VS, a 0.1 mF to 1.0 mF ceramic
capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG).
4 CO Logic level control input produces complementary output states − no inversion at TG; inversion at BG.
5 EN Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation
ensues. No connect defaults EN high. Note: maximum high input is 5.0 V.
6 VS Power supply input. A 0.1 mF to 1.0 mF ceramic capacitor should be connected from this pin to PGND.
7 BG Driver output to the low−side (synchronous rectifier) MOSFET gate.
8
PGND
Ground.
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NCP5355
MAXIMUM RATINGS
Rating
Value
Unit
Operating Junction Temperature, TJ
Package Thermal Resistance: SOIC−8
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA
Internally Limited
°C
45 °C/W
165 °C/W
Package Thermal Resistance: SOIC−8 EP
Junction−to−Ambient, RqJA (Note 1)
50 °C/W
Storage Temperature Range, TS
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2)
−65 to 150
230 peak
°C
°C
JEDEC Moisture Sensitivity
1−
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Ratings applies when soldered to an appropriate thermal area on the PCB.
2. 60 seconds maximum above 183°C.
MAXIMUM RATINGS
Pin Symbol
Pin Name
VS Main Supply Voltage Input
VMAX
15 V
VMIN
−0.3 V
BST
DRN
TG
BG
CO
EN
PGND
Bootstrap Supply Voltage 30 V wrt/PGND
Input
15 V wrt/DRN
Switching Node
(Bootstrap Supply Return)
26 V
High−Side Driver Output
(Top Gate)
Low−Side Driver Output
(Bottom Gate)
TG and BG Control Input
Enable Input
Ground
30 V wrt/PGND
15 V wrt/DRN
15 V
5.5 V
5.5 V
0V
−0.3 V wrt/DRN
−1.0 V DC
−5.0 V for 100 ns
−6.0 V for 20 ns
−0.3 V wrt/DRN
−0.3 V
−0.3 V
−0.3 V
0V
NOTE: All voltages are with respect to PGND except where noted.
ISOURCE
NA
ISINK
2.0 A Peak (< 100 ms)
250 mA DC
NA 2.0 A Peak (< 100 ms)
250 mA DC
2.0 A Peak (< 100 ms)
250 mA DC
NA
2.0 A Peak (< 100 ms) 2.0 A Peak (< 100 ms)
250 mA DC
250 mA DC
2.0 A Peak (< 100 ms) 2.0 A Peak (< 100 ms)
250 mA DC
250 mA DC
1.0 mA
1.0 mA
1.0 mA
1.0 mA
2.0 A Peak (< 100 ms)
250 mA DC
NA
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