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WJLXT972M PDF даташит

Спецификация WJLXT972M изготовлена ​​​​«Intel» и имеет функцию, называемую «Single-Port 10/100 Mbps PHY Transceiver».

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Номер произв WJLXT972M
Описание Single-Port 10/100 Mbps PHY Transceiver
Производители Intel
логотип Intel логотип 

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WJLXT972M Даташит, Описание, Даташиты
.DataShIPenHetteY4lU®T.cLraoXmnTs9c7e2ivMerSingle-Port 10/100DaMtabshpesetThe Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast
Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It
w provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access
w Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.
w Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is
powered from a single 3.3V power supply.
Applications omCombination 10BASE-T/100BASE-TX
.cNetwork Interface Cards (NICs)
Wireless access points
Network printers
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
Product Features t4U3.3V Operation
IEEE 802.3-compliant 10BASE-T or
e100BASE-TX with integrated filters
Auto-negotiation and parallel detection
eMII interface with extended register
capability
hRobust baseline wander correction
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
Integrated, programmable LED drivers
48-pin Low-profile Quad Flat Package
taSRESET_L
ADDR[1:0]
aMDIO
MDC
.DTX_EN
TXD[3:0]
TX_CLK
wLED/CFG[3:1]
wCOL
mRX_CLK
w oRXD[3:0]
.cRX_DV
CRS
t4URX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
+
TP
Driver -
TP Out
JTAG
Collision
Detect
Clock
Generator
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
Manchester
10 Decoder
100
Decoder &
Descrambler
Media
Select
OSP
Slicer
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
+
10BT
-
TP In
VCC
GND
REFCLK/XI
XO
TPOP
TPON
TDI
5 TDO
TMS
TCK
TRST_L
TPIP
TPIN
B3387-13
.DataSheeDocument Number: 302875-004
wwwRevision Date: February 18, 2005









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WJLXT972M Даташит, Описание, Даташиты
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or
in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
2 Datasheet
Document Number: 302875-004
Revision Date: 27-Oct-2005









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WJLXT972M Даташит, Описание, Даташиты
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
Contents
1.0 Introduction to This Document ......................................................................................... 13
1.1 Document Overview ............................................................................................13
1.2 Related Documents............................................................................................. 13
2.0 Block Diagram for Intel® LXT972M Transceiver............................................................... 14
3.0 Pin Assignments for Intel® LXT972M Transceiver ...........................................................15
4.0 Signal Descriptions for Intel® LXT972M Transceiver ....................................................... 18
5.0 Functional Description...................................................................................................... 24
5.1 Device Overview .................................................................................................25
5.1.1 Comprehensive Functionality ................................................................. 25
5.1.2 Optimal Signal Processing Architecture ................................................. 25
5.2 Network Media / Protocol Support.......................................................................26
5.2.1 10/100 Network Interface .......................................................................26
5.2.2 MII Data Interface ................................................................................... 28
5.2.3 Configuration Management Interface ..................................................... 28
5.3 Operating Requirements .....................................................................................31
5.3.1 Power Requirements ..............................................................................31
5.3.2 Clock Requirements ............................................................................... 31
5.4 Initialization.......................................................................................................... 32
5.4.1 MDIO Control Mode and Hardware Control Mode .................................34
5.4.2 Reduced-Power Modes .......................................................................... 34
5.4.3 Reset for Intel® LXT972M Transceiver................................................... 34
5.4.4 Hardware Configuration Settings ...........................................................36
5.5 Establishing Link .................................................................................................37
5.5.1 Auto-Negotiation.....................................................................................37
5.5.2 Parallel Detection ................................................................................... 38
5.6 MII Operation....................................................................................................... 39
5.6.1 MII Clocks............................................................................................... 40
5.6.2 Transmit Enable .....................................................................................41
5.6.3 Receive Data Valid ................................................................................. 41
5.6.4 Carrier Sense ......................................................................................... 42
5.6.5 Error Signals........................................................................................... 42
5.6.6 Collision .................................................................................................. 42
5.6.7 Loopback................................................................................................ 43
5.7 100 Mbps Operation ............................................................................................44
5.7.1 100BASE-X Network Operations ...........................................................44
5.7.2 Collision Indication ................................................................................. 47
5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 48
5.8 10 Mbps Operation.............................................................................................. 53
5.8.1 10BASE-T Preamble Handling ............................................................... 53
5.8.2 10BASE-T Carrier Sense .......................................................................53
5.8.3 10BASE-T Dribble Bits ........................................................................... 53
5.8.4 10BASE-T Link Integrity Test ................................................................. 54
5.8.5 Link Failure ............................................................................................. 54
Datasheet
Document Number: 302875-004
Revision Date: 27-Oct-2005
3










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Номер в каталогеОписаниеПроизводители
WJLXT972ASingle-Port 10/100 Mbps PHY TransceiverIntel
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