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PDF HI20201 Data sheet ( Hoja de datos )
| Número de pieza | HI20201 | |
| Descripción | 10-Bit Ultra High Speed D/A Converter | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI20201 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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TM
t4U.com HI20201August 1997
10-Bit, 160 MSPS,
Ultra High Speed D/A Converter
heeFeatures
S• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 160MHz
ta• Resolution (HI20201). . . . . . . . . . . . . . . . . . . . . . . . 10-Bit
a• Differential Linearity Error . . . . . . . . . . . . . . . . . . .0.5 LSB
.D• Low Glitch Noise
w• Analog Multiplying Function
w• Low Power Consumption . . . . . . . . . . . . . . . . . . . 420mW
w • Evaluation Board Available
m• Direct Replacement for Sony CX20201-1, CX20202-1
Applications
o• Wireless Communications
.c• Signal Reconstruction
• Direct Digital Synthesis
• High Definition Video Systems
U• Digital Measurement Systems
• Radar
Description
The HI20201 is a 160MHz ultra high speed D/A converter. The
converter is based on an R/2R switched current source archi-
tecture that includes an input data register with a complement
feature and is Emitter Coupled Logic (ECL) compatible.
The HI20201 is available in a commercial temperature range
and offered in a 28 lead plastic SOIC (300 mil) and a 28 lead
plastic DIP package.
Ordering Information
PART
NUMBER
HI20201JCB
HI20201JCP
HI20201-EV
TEMP.
RANGE (oC) PACKAGE
PKG. NO.
-20 to 75 28 Ld SOIC M28.3A-S
-20 to 75 28 Ld PDIP E28.6A-S
25 Evaluation Kit
www.DataSheet4 .comPinout
HI20201
(PDIP, SOIC)
TOP VIEW
(MSB) D9 1
D8 2
D7 3
D6 4
D5 5
D4 6
D3 7
D2 8
D1 9
(LSB) D0 10
NC 11
NC 12
CLK 13
CLK 14
28 AVSS
27 VREF
26 AVEE
25 NC
24 NC
23 NC
22 NC
21 NC
20 IOUT
19 NC
18 AVSS
17 DVSS
16 COMPL
15 DVEE
ww.DataSheet4UCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
w1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
FN3581.5
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1197
1 page  
Typical Performance Curves
-2.0
TA = 25oC, VEE = -5.2V
LINEAR AREA
-1.0
RL = 10kΩ
RL = 75Ω
HI20201
1.05
1.00
RL = 10kΩ
RL = 75Ω
0
0.5 1.0
VREF - VEE (V)
FIGURE 2. VO(FS) RATIO vs (VREF - VEE)
0.95
-20 0
20 40 60 80
1.5 AMBIENT TEMPERATURE (oC)
FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT
TEMPERATURE
0
GAIN
0
PHASE
-10 -90
-180
-20
10K
100K
1M
10M
100M
MULTIPLYING INPUT SIGNAL FREQUENCY (Hz)
FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING
INPUT SIGNAL FREQUENCY
10.0 fCLK = 100MHz
8.0
6.0
4.0
2.0
-50 0 50 100
CASE TEMPERATURE (oC)
FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE (FULL
SCALE - 1023mV)
1201
5 Page 
Test Circuits (Continued)
Measuring Settling Time
Settling time is measured as follows. The relationship
between V and V0(FS) as shown in the D/A output waveform
in Figure 12 is expressed as
V = V0(FS) (1 - e-tτ).
The settling time for respective accuracy of 10, 9 and 8-bit is
specified as
V = 0.9995 V0(FS)
V = 0.999 V0(FS)
V = 0.999 V0(FS)
which results in the following:
tS
tS
tS
=
=
=
7.60τ
6.93τ
6.24τ
for 10-bit,
for 9-bit, and
for 8-bit,
Rise time (tr) and fall time (tf) are defined as the time interval
to slew from 10% to 90% of full scale voltage (V0(FS)):
V = 0.1 V0(FS)
V = 0.9 V0(FS)
and calculated as tr = tf = 2.20τ.
The settling time is obtained by combining these expressions:
tS = 3.45tr for 10-bit,
tS = 3.15tr for 9-bit, and
tS = 6.24tr for 8-bit
“1”
CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
τ
V0(FS) = 1V
V
τ
FIGURE 12. D/A OUTPUT WAVEFORM
Adjust so that the voltage at point B
becomes -1V with no AC input.
10kΩ
0.047µ
0.1µF
OSC
51
A
-5.2V
B TO SCOPE
-5.2V
A GND D GND
FIGURE 13A.
1207
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HI20201.PDF ] | |
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