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S21152 PDF даташит

Спецификация S21152 изготовлена ​​​​«Intel» и имеет функцию, называемую «PCI to PCI Bridge».

Детали детали

Номер произв S21152
Описание PCI to PCI Bridge
Производители Intel
логотип Intel логотип 

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S21152 Даташит, Описание, Даташиты
21e1t45U2.cPomCI-to-PCI BridgeDatasheet
ataSheProduct Features
w.D Complies fully with Revision 2.1 of the PCI
w Local Bus Specification,
w Complies fully with Revision 1.1 of the
PCI-to-PCI Bridge Architecture
mSpecification,
Complies fully with the Advanced
oConfiguration Power Interface (ACPI)
Specification
.cComplies fully with the PCI Power
Management Specification, Revision 1.01
UImplements delayed transactions for all PCI
configuration, I/O, and memory read
t4commands—up to three transactions
simultaneously in each direction
Allows 88 bytes of buffering (data and
eaddress) for posted memory write
commands in each direction—up to three
etransactions simultaneously in each
direction
hAllows 72 bytes of read data buffering in
each direction
SProvides concurrent primary and secondary
bus operation to isolate traffic
taProvides five secondary clock outputs
— Low skew, permitting direct drive of
aoption slots
— Individual clock control through
.Dconfiguration space
Provides arbitration support for four
secondary bus devices
— A programmable 2-level arbiter
— Hardware disable control, permitting use
of an external arbiter
Provides enhanced address decoding
— A 32-bit I/O address range
— A 32-bit memory-mapped I/O address
range
— A 64-bit prefetchable memory address
range
— ISA-aware mode for legacy support in
the first 64 KB of I/O address range
— VGA addressing and VGA palette
snooping support
Supports PCI transaction forwarding for the
following commands
— All I/O and memory commands
— Type 1 to Type 1 configuration
commands
— Type 1 to Type 0 configuration
commands (downstream only)
— All Type 1 to special cycle configuration
commands
Includes downstream lock support
Supports both 5 V and 3.3 V signaling
environments
w1. 21152–AB and later revisions only. The 21152–AA does not implement this feature.
ww .DataSheet4U.comOrder Number: 278060, Revision: 002US
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S21152 Даташит, Описание, Даташиты
INFORMATIONLegalLines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or
in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
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*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation. All Rights Reserved.
April 2005
2
21152 PCI-to-PCI Bridge
Order Number: 278060, Revision: 002US
Datasheet









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S21152 Даташит, Описание, Даташиты
Shortened Product Name
Contents
1.0 Introduction.................................................................................................................................... 7
2.0 Signal Pins ...................................................................................................................................13
3.0 Pin Assignment ...........................................................................................................................23
4.0 PCI Bus Operation.......................................................................................................................31
5.0 Address Decoding.......................................................................................................................59
6.0 Transaction Ordering ..................................................................................................................69
7.0 Error Handling .............................................................................................................................73
8.0 Exclusive Access ........................................................................................................................87
9.0 PCI Bus Arbitration .....................................................................................................................91
10.0 Clocks...........................................................................................................................................95
11.0 Reset.............................................................................................................................................97
12.0 PCI Power Management ..............................................................................................................99
13.0 Configuration Space Registers ................................................................................................101
14.0 Diagnostic Nand Tree................................................................................................................131
15.0 Electrical Specifications ...........................................................................................................133
16.0 Mechanical Specifications ........................................................................................................139
17.0 Configuration Register Values After Reset .............................................................................141
Figures
1 21152 on the System Board ......................................................................................................... 7
2 21152 with Option Cards ..............................................................................................................8
3 21152 Block Diagram ................................................................................................................... 9
4 21152 Downstream Data Path....................................................................................................11
5 21152 Pinout Diagram ................................................................................................................23
6 Flow-Through Posted Memory Write Transaction ......................................................................35
7 Downstream Delayed Write Transaction ....................................................................................38
8 Fast Back-to-Back Transactions on the Target Bus ...................................................................40
9 Nonprefetchable Delayed Read Transaction..............................................................................44
10 Prefetchable Delayed Read Transaction ....................................................................................45
11 Flow-Through Prefetchable Read Transaction ...........................................................................46
12 Configuration Transaction Address Formats ..............................................................................47
13 Delayed Write Transaction Terminated with Master Abort .........................................................53
14 Delayed Read Transaction Terminated with Target Abort..........................................................56
15 I/O Transaction Forwarding Using Base and Limit Addresses ...................................................60
Datasheet
21152 PCI-to-PCI Bridge
Order Number: 278060, Revision: 002US
April 2005
3










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