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PDF HD6417750 Data sheet ( Hoja de datos )
| Número de pieza | HD6417750 | |
| Descripción | MICROPROCESSOR | |
| Fabricantes | Hitachi | |
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U.comwww.DataSHhietaecSht4Hi US7u.cp7eor5mH0SReISrCieesngine
t4SH7750, SH7750S, SH7750R
heeHardware Manual
www.DataSADE-602-124E
Rev. 6.0
7/10/2002
Hitachi, Ltd.
www.DataSheet4U.com
1 page  
List of Items Revised or Added for This Version
Section
Page
1.1 SH7750 Series (SH7750, 1
SH7750S, SH7750R)
Features
4 to 8
1.2 Block Diagram
9
1.3 Pin Arrangement
1.4 Pin Functions
2.7 Processor Modes
3.2 Register Descriptions
10 to 12
13 to 40
55
61
62
62
3.3.1 Physical Address
Space
64 to 67
Item
Description
Description amended
and added
Table 1.1 SH7750 Series
Features
Figure 1.1 Block Diagram of
SH7750 Series Functions
Figure 1.2 to 1.4
Table 1.2 to 1.4
Figure 3.2 MMU-Related
Registers
3. Page table entry
assistance register (PTEA)
1. Page table entry high
register (PTEH),
6. MMU control register
(MMUCR)
Description added for
LSI, and description
and Note added for
Clock pulse generator
(CPG)
SH7750 and SH7750S
added to cache memory
Cache memory
[SH7750R] added to
table
Description added for
Direct memory access
controller (DMAC) and
Timer unit (TMU)
SH7750R table added
to Product lineup
Notes 1, 2, 3 added
I cache 8 KB and 0
cache 16 KB deleted
from table
SH7750R added, and
description amended
Table and note
amended
Description deleted
Amended
SH7750R added after
SH7750S
Description added
Description added
Rev. 6.0, 07/02, page v of I
5 Page 
Section
13.2.8 Memory Control
Register (MCR)
Page
355
358
13.2.10 Synchronous DRAM 362 to
Mode Register (SDMR)
364
13.3.1 Endian/Access Size 370
and Data Alignment
371
Item
Bits 15 to 13—Write
Precharge Delay (TRWL2–
TRWL0)
For Synchronous DRAM
Interface
Data Configuration
13.3.2 Areas
382 Area 0, Area 1
13.3.3 SRAM Interface
387
13.3.4 DRAM Interface
13.3.5 Synchronous DRAM
Interface
387 Basic Timing
388, 393 Figures 13.6, 13.11 to 13.13
to 395
395 Read-Strobe Negate Timing
(Setting Only Possible in the
SH7750R)
400 to 408 Figures 13.17 to 13.22
413 Connection of Synchronous
DRAM
415 Address Multiplexing
417 to
428
Figure 13.28 to 13.37
435 Power-On Sequence
Description
Description added
AMX6 description and
Notes amended
Description amended,
and Note added
Description amended
Quadword partially
amended
Description added and
amended
Basic interface changed
to SRAM interface
Description amended
Notes added
Description added and
amended
Notes added
Description added
Description amended
Note added
Newly added
13.3.6 Burst ROM Interface
438 Notes on Changing the Burst Newly added
Length (Variation Only
Possible in the SH7750R)
440 Connecting a 128-Mbit/256- Newly added
Mbit Synchronous DRAM with
64-bit Bus Width
441, 442
Description amended
442 to 444 Figure 13.46 to 13.48
Notes added
Rev. 6.0, 07/02, page xi of I
11 Page | ||
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| PDF Descargar | [ Datasheet HD6417750.PDF ] | |
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