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PDF HD6417709S Data sheet ( Hoja de datos )
| Número de pieza | HD6417709S | |
| Descripción | MICROPROCESSOR | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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omTo all our customers
U.cRegarding the change of names mentioned in the document, such as
t4Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
SheeThe semiconductor operations of Mitsubishi Electric and Hitachi were
tatransferred to Renesas Technology Corporation on April 1st 2003.
aThese operations include microcomputer, logic, analog and discrete devices,
.Dand memory chips other than DRAMs (flash memory, SRAMs etc.)
w Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
w and other Hitachi brand names are mentioned in the document, these names
w have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
mcontents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
.coRenesas Technology Home Page: www.renesas.com
et4URenesas Technology Corp.
Customer Support Dept.
www.DataSheApril 1, 2003
Renesas Technology Cwowrpw..DataSheet4U.com
1 page  
• User manuals for development tools
Name of Document
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual
Simulator/Debugger User’s Manual
Hitachi Embedded Workshop User’s Manual
• Application note
Name of Document
C/C++ Compiler Guide
Document No.
ADE-702-246
ADE-702-186
ADE-702-201
Document No.
ADE-xxx-xxx
5 Page 
10.1.1 Features ................................................................................................................. 227
10.1.2 Block Diagram ...................................................................................................... 229
10.1.3 Pin Configuration .................................................................................................. 230
10.1.4 Register Configuration .......................................................................................... 232
10.1.5 Area Overview ...................................................................................................... 233
10.1.6 PCMCIA Support.................................................................................................. 236
10.2 BSC Registers .................................................................................................................... 239
10.2.1 Bus Control Register 1 (BCR1) ............................................................................ 239
10.2.2 Bus Control Register 2 (BCR2) ............................................................................ 243
10.2.3 Wait State Control Register 1 (WCR1)................................................................. 244
10.2.4 Wait State Control Register 2 (WCR2)................................................................. 245
10.2.5 Individual Memory Control Register (MCR)........................................................ 249
10.2.6 PCMCIA Control Register (PCR)......................................................................... 252
10.2.7 Synchronous DRAM Mode Register (SDMR) ..................................................... 256
10.2.8 Refresh Timer Control/Status Register (RTCSR) ................................................. 257
10.2.9 Refresh Timer Counter (RTCNT) ......................................................................... 259
10.2.10 Refresh Time Constant Register (RTCOR) .......................................................... 260
10.2.11 Refresh Count Register (RFCR) ........................................................................... 260
10.2.12 Cautions on Accessing Refresh Control Related Registers .................................. 261
10.2.13 MCS0 Control Register (MCSCR0) ..................................................................... 262
10.2.14 MCS1 Control Register (MCSCR1) ..................................................................... 263
10.2.15 MCS2 Control Register (MCSCR2) ..................................................................... 263
10.2.16 MCS3 Control Register (MCSCR3) ..................................................................... 263
10.2.17 MCS4 Control Register (MCSCR4) ..................................................................... 263
10.2.18 MCS5 Control Register (MCSCR5) ..................................................................... 263
10.2.19 MCS6 Control Register (MCSCR6) ..................................................................... 263
10.2.20 MCS7 Control Register (MCSCR7) ..................................................................... 263
10.3 BSC Operation.................................................................................................................... 264
10.3.1 Endian/Access Size and Data Alignment.............................................................. 264
10.3.2 Description of Areas.............................................................................................. 269
10.3.3 Basic Interface....................................................................................................... 272
10.3.4 Synchronous DRAM Interface.............................................................................. 280
10.3.5 Burst ROM Interface ............................................................................................. 309
10.3.6 PCMCIA Interface ................................................................................................ 312
10.3.7 Waits between Access Cycles ............................................................................... 324
10.3.8 Bus Arbitration...................................................................................................... 325
10.3.9 Bus Pull-Up ........................................................................................................... 326
10.3.10 MCS[0] to MCS[7] Pin Control............................................................................ 328
Section 11 Direct Memory Access Controller (DMAC) .......................................... 331
11.1 Overview ............................................................................................................................ 331
11.1.1 Features ................................................................................................................. 331
11.1.2 Block Diagram ...................................................................................................... 333
vi
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