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PDF NP4201MF02 Data sheet ( Hoja de datos )
| Número de pieza | NP4201MF02 | |
| Descripción | COSMOPLASMA | |
| Fabricantes | NEC | |
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DATA SHEET
COLOR PLASMA DISPLAY MODULE
NP4201MF02
106 cm (42-inch), Wide Screen (853 × 480 Pixels), Digital Module
Digital RGB signal, 8-bit signal each
DESCRIPTION
The NP4201MF02 is a 42-inch wide color plasma display module with a resolution of 853(H) × 480(V) pixels.
The display offers vibrant colors we reproduced in a thin and low profile package. This device uses AC plasma
technology by NEC and includes an 8-bit digital interface.
FEATURES
• Applied Capsulated Color Filter (CCF) technology, developed at NEC, which offers a high quality image
match for CRT display. To offer remarkably pure colors, the color plasma display panel uses extremely clear,
thin capsulated color filters to cut unnecessary light as the plasma discharges.
• Contrast ratio of 350:1 is achieved through a new driving method, which offers improved black levels instead
of toning down the white light emitted.
• Applied Peak Luminance Enhancement (PLE) function which enable the display to operate with the ideal
contrast. The PLE function makes it possible to adjust the average brightness level of the PDP display
automatically in accordance with the average brightness level of an input video signal.
APPLICATIONS
• Wide Screen TV (aspect ratio 16:9)
• Public Information Display
• Video Conference Systems
• Retail
• Education and Training Systems
The information in this document is subject to change without notice.
Document No. EA0353EJ1V0DS00 (1st edition)
Date Published February 1998 P
Printed in Japan
©
1998
1 page  
NP4201MF02
SIGNAL FUNCTION
Symbol
R7 to R0
G7 to G0
B7 to B0
ADCK
HSYNC
VSYNC
M2 to M0
400H
FS
FULH
PSC3 to PSC0
SVFLG
BLKH
SDATA
LE
SCK
PS3 to PS0
HW
VW
ALARM1
ALARM2
Table 3. Interface Signal Function
I/O Function
I 8 bits red video signalNote 1
I 8 bits green video signalNote 1
I 8 bits blue video signalNote 1
I Clock signal which synchronizes to video signal
I Horizontal synchronous signal tw = 4 TADCK min
I Vertical synchronous signal tw = 200 ns min.
I Video mode selection
I Mode signal
I Function selectionNote 2
I Switch for “Full display mode” and “Normal display mode”
I 4 bits PLE control signal (16 steps)
I NEC internal test function mode
I Video blanking and mutingNote 3
I Serial data for display position adjustment
I SDATA latch enable
I SDATA clock
O 4 bits average brightness level signal (16 steps)
O H window display period indication signal
O V window display period indication signal
O Alarm signal for panel broken and failure of internal power-
O source.Note 4
(Remarks)
(R7: MSB, R0: LSB)
(G7: MSB, G0: LSB)
(B7: MSB, B0: LSB)
(positive edge)
(negative pulse)
(negative pulse)
(refer to the following list)
(refer to the following list)
(“L” in normal display mode)
(“H” in full display mode)
(PSC3: MSB, PSC0: LSB)
(“L” in normal display mode)
(“H” in muting)
(total 16 bit: V-7 bit, H-9 bit)
(negative logic)
(latch in positive edge)
(PS3: MSB, PS0: LSB)
(“H” in display period)
(“H” in display period)
(“L” in alarmed status)
MSB : Most Significant Bit
LSB : Least Significant Bit
Notes 1. The RGB video signal should be compensated with Inverse γ circuit before input to the color plasma
display module.
2. In case of normal display mode (aspect ratio = 4:3), gray level in right and left sides of no display
areas can be set with M2-M0 (3 bits) data (While FS = “H” level, gray level is read into the module by
VSYNC pulse).
3. When BLKH input is “H” level, all RGB data is read as “L” level (black color data).
4. When ALARM output turns to “L” level, high voltage power input (Sustain power supply: Vs, and Data
power supply: Vd) should be switched off immediately. When glass panel is broken, high voltage may
occur at the electrode section and cause electric shock. Failure of internal power-source cause over-
power status and gives damage to the display panel and driver-circuits.
5
5 Page 
NP4201MF02
Timing Diagram (Full Display Mode, 480 Lines)
1 V (refer to the Vert. Freq. in Table 4)
VSYNC
PSC3-0
PS3-0 Out
200 ns min.
1000 ns max.
HSYNC
VSYNC
HSYNC
RGB Data
VW Out
1234
tVS
(200 ns min.)
480
1234
480
1234
480
5 ns min.
123
1 H (refer to the Horz. Freq. in Table 4)
479 480
01 2
DV-1 DV
DV (refer to Table 4)
123
479 480
Display Period
1234
HSYNC
ADCK
RGB Data
HW Out
ths
(4 TADCK min.)
5 ns min.
TADCK duty: 40 to 60 % (refer to Table 4, dot-clock freq.)
1234
852 853
01
Dh-1 Dh
Dh (refer to table 4) 15 ns min.
D1 D2 D3 D4
D852 D853
Display Period (with 3 dot clocks delay)
BLKH
123
D1 D2 D3
15 ns min.
Blanking or muting
period
11
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