|
|
PDF NP4203MF02 Data sheet ( Hoja de datos )
| Número de pieza | NP4203MF02 | |
| Descripción | COSMOPLASMA | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NP4203MF02 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
DATA SHEET
COLOR PDP MODULE
NP4203MF02
106 cm (42 inches), Wide Screen (853 u 480 Pixels), Digital Module
Digital 8-bit RGB Signal
DESCRIPTION
The NP4203MF02 is a 42-inch wide color PDP module with a resolution of 853 (H) x 480 (V) pixels. The display
offers vibrant colors reproduced in a thin, low profile package. This device uses AC plasma technology developed
by NEC and includes an 8-bit digital interface.
FEATURES
• CCF (Applied Capsulated Color Filter) technology, developed at NEC, offers a high quality image match for
CRT display. To offer remarkably pure colors, the color plasma display panel uses extremely clear, thin
capsulated color filters to cut unnecessary light as the plasma discharges.
• Contrast ratio of 500:1 (typical value) is achieved through a new driving method, which offers improved black
levels instead of toning down the white light emitted.
• The applied peak luminance enhancement (PLE) function enables the display to operate with ideal contrast.
The PLE function makes it possible to adjust the average brightness level of the PDP display automatically in
accordance with the average brightness level of an input video signal.
APPLICATIONS
• Wide screen TV (aspect ratio 16:9)
• Public information displays
• Video conference systems
• Retail
• Education and training systems
The information in this document is subject to change without notice.
Document No. EA0448EJ1V0DS00 (1st edition)
Date Published July 1999 P
Printed in Japan
©
1999
1 page  
NP4203MF02
SIGNAL FUNCTIONS
Symbol
R7 to R0
G7 to G0
B7 to B0
ADCK
HSYNC
VSYNC
M2 to M0Note 2
400HNote 2
FSNote 2
FULHNote 2
PSC3 to PSC0,
PSCL
SVFLG
BLKH
SDATA
LE
SCK
MS
PS3 to PS0, PSL
HW
VW
ALARM
LVP
Table 3. Interface Signal Function
I/O Function
I 8 bits red video signalNote 1
I 8 bits green video signal Note 1
I 8 bits blue video signal Note 1
I Clock signal which synchronizes to video signal
I Horizontal synchronous signal tw = 4 TADCK min.
I Vertical synchronous signal
tw = 200 ns min.
I These signal inputs are only used in a compatible operation
I with the previous model (NP4201MF02).
I
I
I PLE control signal
Remarks
(R7: MSB; R0: LSB)
(G7: MSB; G0: LSB)
(B7: MSB; B0: LSB)
(negative pulse)
(negative pulse)
(PSC3: MSB*; PSCL: LSB**)
I NEC internal test function mode
I Video blanking and mutingNote 3
I Serial data
I SDATA latch enable
I SDATA clock
I Switch for parallel interface and serial interface mode
O PLE average brightness level signal
O H window display period indication signal
O V window display period indication signal
O Alarm signal for broken panel or failure of internal power
source.Note 4
O Power supply shutdown signal upon alarm statusNote 4
(set to “L” level)
(“H” in muting)
(total 40 bit)
(negative logic)
(latch in positive edge)
(set to “H” level)
(PS3: MSB, PS0: LSB)
(“H” in display period)
(“H” in display period)
(“L” in alarmed status)
(“L” in alarmed status)
*MSB : Most Significant Bit
**LSB : Least Significant Bit
Notes 1. The RGB video signal should be compensated by an Inverse J circuit before being input to the color
plasma display module.
2. These signal inputs are used for parallel interface mode, which is compatible with the previous model
(NP4201MF02), when the “MS” input is set to “L” level.
3. While BLKH input is at “H” level, the entire display area image turns to black color display.
4. When ALARM output turns to “L” level, high voltage power input (Sustain power supply: Vs; data
power supply: Vd) should be switched off immediately. If the glass panel is broken, high voltage may
occur at the electrode section and cause electric shock. Failure of the internal power source causes
over-power status and damages the display panel and driver circuits.
Data Sheet EA0448EJ1V01DS00
5
5 Page 
RGB Data Read Timing by ADCK
RGB Data
Data
NP4203MF02
Data
ADCK
thold
7 ns (max.)
ADCK (Data Cycle Time)
Frequency (MHz)
Cycle time (ns)
20 to 25
50 to 40
26 to 30
39 to 33
31 to 35
32 to 28
36 to 42
27 to 23
thold (ns)
17
12
7
3
Data Sheet EA0448EJ1V01DS00
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NP4203MF02.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NP4203MF02 | COSMOPLASMA | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |