PDF CLA70000 Data sheet ( Hoja de datos )

Número de pieza	CLA70000
Descripción	High Density CMOS Gate Arrays
Fabricantes	Zarlink Semiconductor
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No Preview Available ! ( DataSheet : www.DataSheet4U.com ) CLA70000 Series High Density CMOS Gate Arrays Recent advances in CMOS processing technology and improvements in design architecture have led to the development of a new generation of array-based ASIC products with vastly improved gate integration densities. This family of CLA70000 1 micron CMOS arrays brings considerable advantages to the design of next generation systems combining high performance and high complexity. Features • Low power channelless arrays from 5,000 to 250,000 available gates (5µW / gate / MHz) • 1 micron (0.8 micron effective) twin well epitaxial process • Typical gate delays of 400 ps (NAND2 , Fanout=2) • Comprehensive cell library including DSP, JTAG/BIST and compiled memory cells (ROM blocks to 64K bits and RAM blocks to 16K bits) • Extensive Range of Plastic and Ceramic Packages for both Surface Mount and Through Board Assembly • Flexible I/O structure allows user to define power pad locations • Fully supported on industry standard workstations and in-house software • High drive output stages with slew rate control • Supports JTAG and BIST test philosophies (IEEE 1149-1 Test Procedures) • MIL 883C compliant product available (paragraph 1.2.1) DS2462 ISSUE 3.1 March 1992 Overview The CLA70000 gate array family is Zarlink Semiconductors' sixth generation CMOS gate array product. The family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial CMOS process. The process in conjunction with the advanced layout and route software, offers extremely high packing densities. The array architecture is based upon the earlier well proven CLA60000 series with the emphasis being placed on high speed, high packing density, and provision of comprehensive cell libraries. The cell libraries encompass new DSP and other specialized macros. Full design support is available for major industry standard ASIC design software tools, as well as Zarlink Semiconductor’s proprietary PDS2 design environment. Design support is provided by Zarlink Semiconductor’s design centers, each offering a variety of design routes, which may be customized to individual customer requirements. Product Details The CLA70000 array series is shown below with typical figures given for usable gates. Actual gate utilization is dependent on circuit structure, giving a range of 40 -70% for two layer metallisation. DEVICE NUMBER CLA70000 CLA71000 CLA72000 CLA73000 CLA74000 CLA75000 CLA76000 CLA77000 CLA78000 I/O AND POWER PADS 44 68 84 100 120 160 200 256 304 GATE COMPLEXITY 5K 12K 19K 27K 39K 70K 110K 182K 256K ESTIMATED USABLE GATES 2.5K 6K 9.5K 13.5K 17.5K 31.5K 49.5K 82K 115K www.DataSheet4U.com www.DataSheet4U.com 1 page CLA70000 Series MUXI4TO1 4 to 1 inverting multiplexer MUXI8TO 1 8 to 1 inverting multiplexer CLKA 2CLKA CLKAP CLKAM CLKB CLKBP CLKE1 CLKE2 CLKE3 Basic clock driver Dual basic clock driver Basic clock driver + inverter Basic clock driver + inverter Large clock driver + inverter Large clock driver + inverter Clock driver with enable Clock driver with enable Clock driver with enable TM 2TM BDR Buffered transmission gate Transmission gate for 2 to 1 multiplexing Internal bus driver DL DL2 DLRS DLARS DF DFRS MDF MDFRS M3DF M3DF Data latch Data latch Data latch with set and reset Data latch with set and reset Master-slave D type flip flop Master-slave D type flip flop with set & reset Multiplexed master-slave D type flip flop Multiplexed master-slave D type flip flop with set & reset Multiplexed m/s D type flip flop Multiplexed m/s D type flip flop with set & reset JK JKRS JBARK JBARKRS J-K flip-flop J-K flip-flop with set & reset JBAR-K flip-flop JBAR-K flip-flop with set & reset BDL BDLRS JBARKRS BDF BDFRS BMDF BMDFRS BJBARK BJBARKRS Buffered data latch Buffered data latch with set & reset Buffered data latch with set & reset Buffered master-slave D type flip-flop Buffered master-slave D type flip-flop with set & reset Buffered mux. master-slave D type flip-flop Buffered mux. m/s D type with set & reset Buffered J-K flip-flop Buffered J-K flip-flop with set & reset TRID Tristate driver GND VDD Ground Cell VDD Cell Intermediate Buffer Cells IBCCMOS1 IBCCMOS2 IBTTL1 IBBTL2 IBST1 IBST2 CMOS input buffer + large 2 input NAND gate CMOS input buffer + data latch TTL input buffer + large 2 input NAND gate TTL input buffer + data latch Input Schmitt buffer with CMOS switching levels Input Schmitt buffer with 2V switching levels IBGATE IBCLKB IBDF IBDFA IBSK1 IBSK2 IBSK3 IBTRID IBTRID1 IBTRID2 IBTRID3 IB2BD NAND2/NOR2 gates Large clock driver Master-slave D type flip flop Master-slave D type flip flop Driver with slewed outputs Driver with slewed outputs Driver with slewed outputs Tri-state driver Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Tri-state driver with slewed outputs + 2 inverters Dual high powered inverters DRV3 DRV6 Clock driver Clock driver Pad Input Cells IPNR IPR1P IPR1M IPR2P IPR2M IPR3P IPR3M IPR4P IPR4M Input cell with no pull up or down resistors Input cell with 1KOhm pull up resistor Input cell with 1KOhm pull down resistor Input cell with 2KOhm pull up resistor Input cell with 2KOhm pull down resistor Input cell with 4KOhm pull up resistor Input cell with 4KOhm pull down resistor Input cell with 75KOhm pull up resistor Input cell with 75kOhm pull down resistor Oscillator Cells (crystal) to be defined Pad Output Cells OP1 OP2 OP3 OP6 OP12 Smallest drive output cell Small drive output cell Standard drive output cell Medium drive output cell Large drive output cell OP5B OP11B Standard drive non-inverting output cell Large drive non-inverting output cell OPT1 OPT2 OPT3 OPT6 OPT12 Smallest drive tri-state output cell Small drive tri-state output cell Standard drive tri-state output cell Medium drive tri-state output cell Large drive tri-state output cell OP4B OP10B Standard drive non-inverting tri-state output cell Large drive non-inverting tri-state output cell OPOD1 OPOD2 OPOD3 OPOD6 OPOD12 Smallest drive open-drain output cell Small drive open-drain output cell Standard drive open-drain output cell Medium drive open-drain output cell Large drive open-drain output cell 5 5 Page CLA70000 Series AC Characteristics for Selected Cells The CLA70000 technology library contains all the timing information for each cell in the design library. This information is accessible to the simulator, which calculates propagation delays for all signal paths in the circuit design. The simulator can automatically derate timings according to the various factors such as: Supply voltage variation (from nominal 5V) Junction temperature Processing tolerance - manufacturing spreads Gate fanout - logic loading on gate outputs Interconnection wiring - net loading on gate outputs For initial assessments of feasibility, path delay multipliers can be estimated by referring to the following graphs in conjunction with the appropriate delays in the tables. Normalised Delay Multiplier Vs temperature 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -10 40 90 Temperature °C Figure 6 140 Normalised Delay Multiplier Vs Voltage 1.6 1.4 1.2 1 0.8 3 3.5 4 4.5 5 5.5 Voltage FIgure 7 11 11 Page

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