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PDF HD64F3069 Data sheet ( Hoja de datos )
| Número de pieza | HD64F3069 | |
| Descripción | Hardware Manual | |
| Fabricantes | Renesas | |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
General Precautions on Handling of Product
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
they are used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note:
Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
5 Page 
Item
Page Revisions (See Manual for Details)
Edition
Section 18.1 Features
There are two protection modes
577, Note amended
578 * Not available in the H8/3069F.
2nd
edition
Description amended
• Programming/erasing time
The flash memory programming time is 3ms
(typ) in 128-byte simultaneous programming
and 25ms per byte. The erasing time is
1000ms (typ) per block.
• Number of programming
The number of flash memory programming
can be up to minimum 100 times.
Section 18.2.2 Operating Mode 581
Table 18.1 Location of FWE and MD
Pins and Operating Modes
Pin name amended
RES
2nd
edition
Section 18.3 Pin Configuration
Table 18.3 Pin Configuration
587 Abbreviation name amended
RES
2nd
edition
Section 18.4.1 Registers
591 Table amended
Table 18.5 Register/Parameter and
Target Mode
FMATS
FTDAR
DPFR
FPFR
FPEFEQ
—
—
—
— *1 *1 *2 —
——
— ——
——
— ——
——
— — ——
2nd
edition
Section 18.4.5 Flash Vector
609, Description amended
Address Control Register (FVACR) 610 FVADRR to FVADRL
2nd
edition
Section 18.5.2 User Program Mode 617
Figure 18.10 RAM Map when
Programming/Erasing is Executed
Figure amended
Area that can be
used by user
FTDAR setting+2048
2nd
edition
RAMEND(H'FFFF1F)
Programming Procedure in User
Program Mode (c)
619 Description amended
2nd
NMI requests are discarded if the FVACR edition
register value is H'00. However, if H'80 has
been written to the FVACR register, they are
held and the NMI interrupts are generated
when processing returns to the user
procedure program.
Programming Procedure in User
Program Mode (f)
620 Description amended
2nd
The current frequency of the CPU clock is set edition
to the FPEFEQ parameter (general register:
ER0).
11 Page | ||
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| PDF Descargar | [ Datasheet HD64F3069.PDF ] | |
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