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PDF 8086 Data sheet ( Hoja de datos )
| Número de pieza | 8086 | |
| Descripción | 16-Bit HMOS Microprocessor | |
| Fabricantes | Intel | |
| Logotipo |  |
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 1. Datasheet - CMOS 16-Bit Microprocessor  Hay una vista previa y un enlace de descarga de 8086 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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8086
16-BIT HMOS MICROPROCESSOR
8086 8086-2 8086-1
Y Direct Addressing Capability 1 MByte
of Memory
Y Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y 14 Word by 16-Bit Register Set with
Symmetrical Operations
Y 24 Operand Addressing Modes
Y Bit Byte Word and Block Operations
Y 8 and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Y Range of Clock Rates
5 MHz for 8086
8 MHz for 8086-2
10 MHz for 8086-1
Y MULTIBUS System Compatible
Interface
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
Y Available in 40-Lead Cerdip and Plastic
Package
(See Packaging Spec Order 231369)
The Intel 8086 high performance 16-bit CPU is available in three clock rates 5 8 and 10 MHz The CPU is
implemented in N-Channel depletion load silicon gate technology (HMOS-III) and packaged in a 40-pin
CERDIP or plastic package The 8086 operates in both single processor and multiple processor configurations
to achieve high performance levels
Figure 1 8086 CPU Block Diagram
231455 – 1
40 Lead
231455 – 2
Figure 2 8086 Pin
Configuration
September 1990
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Order Number 231455-005
1 page  
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8086
Symbol
QS1 QS0
Pin No
24 25
Table 1 Pin Description (Continued)
Type
O
Name and Function
QUEUE STATUS The queue status is valid during the CLK cycle after
which the queue operation is performed
QS1 and QS0 provide status to allow external tracking of the internal
8086 instruction queue
QS1
0 (LOW)
0
1 (HIGH)
1
QS0 Characteristics
0 No Operation
1 First Byte of Op Code from Queue
0 Empty the Queue
1 Subsequent Byte from Queue
The following pin function descriptions are for the 8086 in minimum mode (i e MN MX e VCC) Only the pin
functions which are unique to minimum mode are described all other pin functions are as described above
M IO
WR
INTA
ALE
DT R
DEN
HOLD
HLDA
28 O STATUS LINE logically equivalent to S2 in the maximum mode It is used to
distinguish a memory access from an I O access M IO becomes valid in
the T4 preceding a bus cycle and remains valid until the final T4 of the cycle
(M e HIGH IO e LOW) M IO floats to 3-state OFF in local bus ‘‘hold
acknowledge’’
29 O WRITE indicates that the processor is performing a write memory or write
I O cycle depending on the state of the M IO signal WR is active for T2 T3
and TW of any write cycle It is active LOW and floats to 3-state OFF in
local bus ‘‘hold acknowledge’’
24 O INTA is used as a read strobe for interrupt acknowledge cycles It is active
LOW during T2 T3 and TW of each interrupt acknowledge cycle
25 O ADDRESS LATCH ENABLE provided by the processor to latch the
address into the 8282 8283 address latch It is a HIGH pulse active during
T1 of any bus cycle Note that ALE is never floated
27 O DATA TRANSMIT RECEIVE needed in minimum system that desires to
use an 8286 8287 data bus transceiver It is used to control the direction of
data flow through the transceiver Logically DT R is equivalent to S1 in the
maximum mode and its timing is the same as for M IO (T e HIGH R e
LOW ) This signal floats to 3-state OFF in local bus ‘‘hold acknowledge’’
26 O DATA ENABLE provided as an output enable for the 8286 8287 in a
minimum system which uses the transceiver DEN is active LOW during
each memory and I O access and for INTA cycles For a read or INTA cycle
it is active from the middle of T2 until the middle of T4 while for a write cycle
it is active from the beginning of T2 until the middle of T4 DEN floats to 3-
state OFF in local bus ‘‘hold acknowledge’’
31 30 I O HOLD indicates that another master is requesting a local bus ‘‘hold ’’ To be
acknowledged HOLD must be active HIGH The processor receiving the
‘‘hold’’ request will issue HLDA (HIGH) as an acknowledgement in the
middle of a T4 or Ti clock cycle Simultaneous with the issuance of HLDA
the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will LOWer the HLDA and when the
processor needs to run another cycle it will again drive the local bus and
control lines Hold acknowledge (HLDA) and HOLD have internal pull-up
resistors
The same rules as for RQ GT apply regarding when the local bus will be
released
HOLD is not an asynchronous input External synchronization should be
provided if the system cannot otherwise guarantee the setup time
5
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8086
MASKABLE INTERRUPT (INTR)
The 8086 provides a single interrupt request input
(INTR) which can be masked internally by software
with the resetting of the interrupt enable FLAG
status bit The interrupt request signal is level trig-
gered It is internally synchronized during each clock
cycle on the high-going edge of CLK To be re-
sponded to INTR must be present (HIGH) during
the clock period preceding the end of the current
instruction or the end of a whole move for a block-
type instruction During the interrupt response se-
quence further interrupts are disabled The enable
bit is reset as part of the response to any interrupt
(INTR NMI software interrupt or single-step) al-
though the FLAGS register which is automatically
pushed onto the stack reflects the state of the proc-
essor prior to the interrupt Until the old FLAGS reg-
ister is restored the enable bit will be zero unless
specifically set by an instruction
During the response sequence (Figure 6) the proc-
essor executes two successive (back-to-back) inter-
rupt acknowledge cycles The 8086 emits the LOCK
signal from T2 of the first bus cycle until T2 of the
second A local bus ‘‘hold’’ request will not be hon-
ored until the end of the second bus cycle In the
second bus cycle a byte is fetched from the external
interrupt system (e g 8259A PIC) which identifies
the source (type) of the interrupt This byte is multi-
plied by four and used as a pointer into the interrupt
vector lookup table An INTR signal left HIGH will be
continually responded to within the limitations of the
enable bit and sample period The INTERRUPT RE-
TURN instruction includes a FLAGS pop which re-
turns the status of the original interrupt enable bit
when it restores the FLAGS
HALT
When a software ‘‘HALT’’ instruction is executed the
processor indicates that it is entering the ‘‘HALT’’
state in one of two ways depending upon which
mode is strapped In minimum mode the processor
issues one ALE with no qualifying bus control sig-
nals In maximum mode the processor issues ap-
propriate HALT status on S2 S1 and S0 and the
8288 bus controller issues one ALE The 8086 will
not leave the ‘‘HALT’’ state when a local bus ‘‘hold’’
is entered while in ‘‘HALT’’ In this case the proces-
sor reissues the HALT indicator An interrupt request
or RESET will force the 8086 out of the ‘‘HALT’’
state
READ MODIFY WRITE (SEMAPHORE)
OPERATIONS VIA LOCK
The LOCK status information is provided by the
processor when directly consecutive bus cycles are
required during the execution of an instruc-
tion This provides the processor with the capability
of performing read modify write operations on
memory (via the Exchange Register With Memory
instruction for example) without the possibility of an-
other system bus master receiving intervening mem-
ory cycles This is useful in multi-processor system
configurations to accomplish ‘‘test and set lock’’ op-
erations The LOCK signal is activated (forced LOW)
in the clock cycle following the one in which the soft-
ware ‘‘LOCK’’ prefix instruction is decoded by the
EU It is deactivated at the end of the last bus cycle
of the instruction following the ‘‘LOCK’’ prefix in-
struction While LOCK is active a request on a RQ
GT pin will be recorded and then honored at the end
of the LOCK
Figure 6 Interrupt Acknowledge Sequence
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231455 – 9
11
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| PDF Descargar | [ Datasheet 8086.PDF ] | |
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