|
|
PDF HPC36400E Data sheet ( Hoja de datos )
| Número de pieza | HPC36400E | |
| Descripción | (HPC36400E / HPC46400E) High-Performance Communications MicroController | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HPC36400E (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
PRELIMINARY
November 1992
HPC36400E HPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400 Features have
been added to support V 120 the 8-bit mode has been en-
hanced to support all instructions and the UART has been
changed to provide more flexibility and power The
HPC46400E is fully upward compatible with the HPC16400
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels 4
channel DMA controller to facilitate data flow for the HDLC
channels programmable serial interface and UART
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC) Multiple address
recognition modes and both bit and byte modes of opera-
tion are supported
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages
Features
Y HPCTM family core features
16-bit data bus ALU and registers
64 kbytes of external memory addressing
FAST 20 0 MHz system clock
Four 16-bit timer counters with WATCHDOGTM logic
MICROWIRE PLUSTM serial I O interface
CMOS low power with two power save modes
Y Two full duplex HDLC channels
Optimized for ISDN X 25 V 120 and LAPD
applications
Programmable frame address recognition
Up to 4 65 Mbps serial data rate
Built in diagnostics
Synchronous bypass mode
Optional CRC generation
Received CRC bytes can be read by the CPU
Y Four channel DMA controller
Y 8- or 16-bit external data bus
Y UART
Full duplex
7 8 or 9 data bits
Even odd mark space or no parity
7 8 1 or 2 stop bit generation
Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
Synchronous and asynchronous modes of operation
Y Serial Decoder
Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
Optional rate adaptation of 64 kbit s data rate to
56 kbit s
Y Over Mbyte of extended addressing
Y Easy interface to National’s DASL ‘U’ and ‘S’ trans-
ceivers TP3400 TP3410 and TP3420
Y Commercial (0 C to a70 C) and industrial (b40 C to
a85 C)
Block Diagram
TapePak and TRI-STATE are registered trademarks of National Semiconductor Corporation
HPCTM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation
IBM PC-AT are registered trademarks of International Business Machines Corporation
Sun is a registered trademark of Sun Microsystems
SunOSTM is a trademark of Sun Microsystems
UNIX is a registered trademark of AT T Bell Laboratories
C1995 National Semiconductor Corporation TL DD10422
www.DataSheet4U.com
TL DD 10422 – 1
RRD-B30M115 Printed in U S A
1 page  
www.DataSheet4U.com
Timing Waveforms
Rise Fall Time
Duty Cycle
TL DD 10422 – 2
FIGURE 1 CKI Input Signal
TL DD 10422 – 3
TL DD 10422 – 4
Note AC testing inputs are driven at VIH for a logic ‘‘1’’ and VIL for a logic ‘‘0’’ Output timing measurements are made at 2 0V for a logic ‘‘1’’ and at 0 8V for a logic
‘‘0’’
FIGURE 2 Input and Output for AC Tests
FIGURE 3 MICROWIRE Setup Hold Timing
TL DD 10422 – 5
FIGURE 4 CKI CK2 ALE Timing Diagram
TL DD 10422 – 6
www.DataSheet4U.com
FIGURE 5 External Hold Timing
5
TL DD 10422 – 7
5 Page 
www.DataSheet4U.com
Pin Descriptions (Continued)
POWER SUPPLIES
VCC1 VCC2 Positive Power Supply (two pins)
GND
Ground for On-Chip Logic
DGND
Ground for Output Buffers
Note There are multiple electrically connected VCC pins on the chip GND
and DGND are electrically isolated All VCC pins and all ground pins
must be used
CLOCK PINS
CKI The System Clock Input
CKO
The System Clock Output (Inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal
CK2
Clock Output (CKI divided by 2)
Connection Diagrams
OTHER PINS
WO This is an active low open drain output which
signals an illegal situation has been detected
by the WATCHDOG logic
ST1 Bus Cycle Status Output indicates first op-
code fetch
ST2 Bus Cycle Status Output indicates machine
states (skip and interrupt)
RESET
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode
RDY HLD
Has two uses selected by a software bit
This pin is either a READY input to extend
the bus cycle for slower memories or a
HOLD-REQUEST input to put the bus in a
high impedance state for external DMA pur-
poses In the second case the I4 pin can be-
come the READY input
Plastic and Leaded Chip Carriers
Top View
See NS Package Number V68A
TL DD 10422 – 18
www.DataSheet4U.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HPC36400E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HPC36400E | (HPC36400E / HPC46400E) High-Performance Communications MicroController | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |