PDF NL17SZ74 Data sheet ( Hoja de datos )

Número de pieza	NL17SZ74
Descripción	Single D Flip Flop
Fabricantes	ON Semiconductor
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No Preview Available ! NL17SZ74 Single D Flip Flop The NL17SZ74 is a high performance, full function Edge triggered D Flip Flop, with all the features of a standard logic device such as the 74LCX74. Features • Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V • Designed for 1.65 V to 5.5 V VCC Operation • 5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic • LVTTL Compatible • LVCMOS Compatible • 24 mA Balanced Output Sink and Source Capability • Near Zero Static Supply Current (10 mA) Substantially Reduces System Power Requirements • Replacement for NC7SZ74 • Tiny Ultra Small Package Only 2.1 X 3.0 mm • High ESD Ratings: 4000 V Human Body Model High ESD Ratings: 200 V Machine Model • Chip Complexity: FET = 64 • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant TRUTH TABLE Inputs Outputs PR CLR CP D Q Q LHXXHL HLXXLH L L XXHH Operating Mode Asynchronous Set Asynchronous Clear Undetermined HH↑ hHL HH↑ l LH Load and Read Register H H ↑ X NC NC Hold H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition NC = No Change X = High or Low Voltage Level and Transitions are Acceptable ↑ = Low−to−High Transition ↑ = Not a Low−to−High Transition For ICC reasons, DO NOT FLOAT Inputs www.onsemi.com US8 US SUFFIX CASE 493 MARKING DIAGRAM MH M G MH = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PINOUT DIAGRAM CP D Q GND 18 27 36 45 VCC PR CLR Q PR D CP CLR LOGIC DIAGRAM 7 25 Q 13 6 Q VCC = 8, GND = 4 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2015 June, 2015 − Rev. 11 1 Publication Order Number: NL17SZ74/D 1 page NL17SZ74 Vcc D 50% ts CP th 50% tw 0V Vcc fmax tPLH, tPHL 0V VOH Q, 50% Q VOL WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns PR 50% CLR Q tPLH 50% 50% tPHL 50% Q PR, CLR tPHL 50% tPLH 50% WAVEFORM 2 − PROPAGATION DELAYS tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns tw 50% trec CP 50% tw WAVEFORM 3 − RECOVERY TIME tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V Figure 1. AC Waveforms VCC PULSE GENERATOR DUT RT CL RL Vcc 0V Vcc 0V VOL VOH Vcc 0V Vcc 0V Figure 2. Test Circuit www.onsemi.com 5 5 Page

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