DataSheet26.com

SDC361 PDF даташит

Спецификация SDC361 изготовлена ​​​​«DDC» и имеет функцию, называемую «(SDC361 / SDC362) 16-Bit 2 Speed Synchro to Digital and Resolver to Digital Converter».

Детали детали

Номер произв SDC361
Описание (SDC361 / SDC362) 16-Bit 2 Speed Synchro to Digital and Resolver to Digital Converter
Производители DDC
логотип DDC логотип 

6 Pages
scroll

No Preview Available !

SDC361 Даташит, Описание, Даташиты
www.DataSheet4U.com
SDC-361/362
16-BIT, TWO SPEED SYNCHRO-TO-DIGITAL
AND RESOLVER-TO-DIGITAL CONVERTER
DESCRIPTION
The SDC-361 is a low-cost, single
module synchro-to-digital (S/D) and
resolver-to-digital (R/D) tracking con-
verter. A unique control transformer
algorithm is used that provides inher-
ently higher accuracy and jitter-free
output. Other features include a BIT
logic signal to indicate proper tracking
and an analog velocity output.
Utilizing a type II servo loop, these
converters have no velocity lag up to
the specified tracking rate, and output
data is always fresh and continuously
available. Each unit is fully trimmed
and requires no adjustment.
APPLICATIONS
The SDC-361 may be used wherever
analog angle data from synchros or
resolvers must be converted rapidly
and accurately to digital form for
transmission, storage and analysis.
Because these units are extremely
rugged and stable, and meet the
requirements of MIL-STD-202E, they
are suitable for the most severe
industrial, commercial and military
applications. Military ground support
and avionics uses include ordnance
control, radar tracking systems, navi-
gation and collision avoidance sys-
tems.
FEATURES
Accuracy: ±1 LSB = ±20 Seconds
SIGNAL AND REF INPUTS:
- Internal Transformer Isolation
- Broadband Input: 350-3000 Hz
or 47-3000 Hz
- All common L-L voltage levels
LOGIC:
- TTL Compatible
- 16-Bit Parallel Binary Angle
Output, and Converter Busy,
Inhibit and BIT
POWER REQUIREMENTS:
- ±15 VDC and +5 VDC
SIN (θ - φ)
SIN 36 (θ - φ)
STICKOFF
36X
SYNCHRO
INPUT
S1
S2
S3
SCOTT-T
SIN 36θ CONTROL
TRANSFORMER
TRANSFORMER
COS 36θ
CT
-
+
CROSS-OVER
DETECTOR
REFERENCE
ISOLATION
TRANSFORMER
RH REF
RL INPUT
36 φ ERROR
36X OR 1X RESOLVER INPUT OPTION:
(θ - φ)
R
ERROR PROCESSOR
VEL VELOCITY
S1
RESOLVER S2
INPUT S3
S4
RESOLVER
ISOLATION
TRANSFORMER
SIN θ
COS θ
36X DIGITAL
MULTIPLIER
φ
AND VOLTAGE
CONTROLLED
OSCILLATOR
INH INHIBIT
CB CONVERTER
BUSY
16 BIT
UP-DOWN COUNTER
om1X
.cSYNCHRO
UINPUT
S1
S2
S3
(CONTAINS ANGLE φ)
φ
SCOTT-T
SIN θ
TRANSFORMER
COS θ
CONTROL
TRANSFORMER
CT
SIN (θ − φ +2.5˚)
CONTAINS 2.5˚
ANGLE OFFSET
www.DataSheet4© 1980, 1999 Data Device Corporation
FIGURE 1. BLOCK DIAGRAM
DIGITAL OUTPUT φ
BITS 1to 16
NOTE: Block Diagram Illustrates
SDC-361. All References to "36X"
are "18X" for SDC-362.









No Preview Available !

SDC361 Даташит, Описание, Даташиты
www.DataSheet4U.com
TABLE 1. SDC-361/362 SPECIFICATIONS
PARAMETER
RESOLUTION
16 bits
VALUE
ACCURACY
SDC-361
SDC-362
±1 LSB ( 20 sec)
±1 LSB ( 40 sec)
TABLE 1. SDC-361/362 SPECIFICATIONS (CONTD)
PARAMETER
DYNAMIC CHARACTERISTICS
(Continued)
VALUE
Velocity Constant
(Type II Servo Loop)
Kv =
SIGNAL AND REFERENCE INPUT
(All inputs transformer isolated.
Other freq. and volt. available.on
special order. )
Signal
Frequency
Range
Synchro Input
90V L-L, 400 Hz (Option H)
90V L-L, 60 Hz (Option I)
11.8V L-L, 400 Hz (Option L)
Resolver Input
90V L-L, 400 Hz (Option H)
26V L-L, 400 Hz (Option I)
11.8V L-L, 400 Hz (Option L)
350-3000 Hz
47-3000 Hz
350-3000 Hz
350-3000 Hz
350-3000 Hz
350-3000 Hz
Signal Input
Impedance
(L-L Balanced,
Resistive)
148 Kohm min
148 Kohm min
19 Kohm min
148 Kohm min
42 Kohm min
19 Kohm min
Acceleration Constant
Options H, M, L ( 400 Hz)
Option I ( 60 Hz)
POWER SUPPLIES
Nominal Value
Voltage Range
Max Voltage without Damage
Current
Typical
Maximum
KA = 70,000 Nominal
KA = 4,300 Nominal
+15 V
+11.5 to
+16.5 V
+18 V
-15 V
-11 to
-16.5 V
-18 V
+5 V
+ 4.5 to
+ 5.5 V
+7 V
10 mA
15 mA
35 mA
50 mA
110 mA
150 mA
Reference
Frequency
Range
Reference Input
Impedance
(L-L Balanced,
Resistive)
TEMPERATURE RANGES
Operating
-1 Option
-3 Option
-55°C to + 105°C
0°C to + 70°C
Reference Input
(Option H, I )
(Option M, L)
40-150 V rms 300 Kohm min
10- 50 V rms 80 Kohm min
Storage
PHYSICAL CHARACTERISTICS
-55°C to + 125°C
DIGITAL INPUT/OUTPUT
Size 3.125 x 2.625 x 0.82 inches
Logic Type
TTL
(79.4 x 66.7 x 20.8 mm)
Inhibit Input (INH) Loading
Logic “0” inhibits, 0.2 Std TTL
loads plus 18 Kohm min
pull-up resistor to +5 V supply.
Weight
7 oz
(200 g)
Outputs
16 Parallel data Bits
Converter Busy (CB)
Natural binary angle; pos. logic
1-2.5 µsec positive pulse,
data changes on leading edge
INTRODUCTION
The operation of a two speed S/D is essentially the same as a
Drive Capabilitity
2 Std TTL loads (Consult factory
single speed module, except there are two control transformers
BIT (Bilt In Test)
for 5 Std load capability)
Logic 0 = normal tracking
Logic 1 = not tracking within
fine speed range
(CT) which generate two error voltages. These two CTs are fed
by a common up-down counter. The counter data is multiplied by
36 for an SDC-361 and 18 for an SDC-362 to generate the fine
speed CT. Assuming an off-null condition as when the system is
ANGULAR VELOCITY OUTPUT
Scale Factor
Range
Loading
DYNAMIC CHARACTERISTICS
±1.0 VDC ±30% for 100°/sec
at 400 Hz
±1.0 VDC ±30% for 25°/sec
at 60 Hz
±10 VDC min
±10 Kohm max
initially energized, the crossover detector feeds the coarse (1X)
CT error signal output to the demodulator and error processor.
The converter seeks a null as it would for a single speed S/D. As
null is approached (to within 2.5° nominally) the coarse CT out-
put drops below a preset threshold and the crossover detector
then switches the fine CT error signal (36X for SDC-361, 18X for
SDC-362) into the demodulator and error processor.
Input Rate for Full Velocity
Options H, M, L (400 Hz)
Option I (60 Hz)
0-1000°/sec minimum
0-250°/sec minimum
Acceleration for 1 LSB Lag
mOptions H, M, L(400 Hz)
oOption I ( 60 Hz)
.cSettling Time
UFor Normal Tracking
t4(Up to specified Input Rate)
eFor 179° Step Change
e(Typical Values)
hOptions H, M, L (400 Hz)
Settling to 1 LSB
SSettling to Final Value
taOptions I (60 Hz)
aSettling to 1 LSB
www.DSettling to Final Value
384°/sec² typ
23°/sec² typ
No Lag Error
400 msec
480 msec
1400 msec
1800 msec
Since the counter angle θ is multiplied by 36X for SDC-361, and
18X for SDC-362, the gradient of the fine speed CT is 36X the
coarse output CT for the SDC-361, and 18X for the coarse out-
put CT for the SDC-362. The servo loop then seeks a finer null,
using the fine speed CT error signal. The converter continues to
use the fine error signal for continuous tracking, and only switch-
es back to the coarse signal when the coarse error exceeds the
crossover threshold. To eliminate false stable nulls at 180°, an
angle offset and stickoff voltage are introduced in the coarse
channel. The ±15 V power supplies can vary over their specified
ranges with no change in the converter specifications except for
a proportional change in the maximum ± tracking rates. When
testing or evaluating the converters, it is advisable to limit the
current to each of the three power supplies. Set each current
limit to 50% greater than the maximum current listed for that sup-
ply in TABLE 1.
2









No Preview Available !

SDC361 Даташит, Описание, Даташиты
www.DataSheet4U.com
To prevent damage to the input transformers, the maximum volt-
age should not exceed the specified input voltage by more than
30%. The maximum common mode voltage (DC plus recurrent
AC peak) should not exceed 500 V.
DIGITAL INPUTS
Logic inputs are low power Schottky and the can drive remote
loads. The BIT logic output is a built-in-test derived from the
crossover detector. It goes to logic 1 whenever the digital output
is not tracking the input signal within the range of the fine speed
synchro or resolver.
TABLE 2. BIT WEIGHT
BIT
DEG/BIT
MIN/BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
180
90
45
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
10,800
5,400
2,700
1,350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
.66
.33
ANALOG VELOCITY OUTPUT
VEL is a DC voltage proportional to the angular velocity dθ/dt =
dφ/dt. The output is derived from an op-amp with low output
impedance and is short-circuit protected. Other characteristics
are listed in TABLE 1.
DYNAMIC PERFORMANCE
A Type II servo loop (Kv = ) and very large acceleration con-
stants give these converters superior dynamic performance, as
listed in TABLE 1. If the power supply voltages are not the ±15
VDC nominal values, the specified input rates for full accuracy
will increase or decrease in proportion to the fractional change in
voltage. The +15 V supply voltage will determine the maximum
positive velocity. The -15 V supply voltage will determine the
maximum negative velocity.
As long as the maximum tracking rate is not exceeded, there will
be no lag in the converter output. If a step input occurs, as is
likely when the power is initially turned on, the response will be
critically damped. After initial slewing at the maximum tracking
rate of the converter, there is one overshoot which is inherent to
a Type II servo. The overshoot settling to final value is a function
of the small signal settling time.
The loop dynamics of DDC’s tracking S/D converters are
described by the unity feedback configuration shown. The
closed-loop transient response is nominally critically damped,
and all loop dynamics can be determined from the diagram and
formulas given.
TIMING
Whenever an input signal change occurs, the converter changes
the digital angle in steps of 1 LSB, and generates a converter
busy pulse (CB). The output data change is initiated at the lead-
ing edge of the CB pulse, and the output is stable within 0.2 µsec
after the leading edge. Extra CB pulses will not occur if the input
angle changes while the counter is locked by the INH. The sim-
plest method of interfacing with a computer is to transfer data at
a fixed time interval after the inhibit is applied. The converter will
ignore an inhibit applied during the “busy” interval until that inter-
val is over. Timing is as follows: (a) apply the inhibit, (b) wait 0.2
µsec, (c) transfer the data and (d) release the inhibit.
5.5 µsec MIN
DEPENDS ON dθ/dt
CONVERTER “ 1 “
mBUSY (CB)
“0“
.coINHIBIT
U(INH)
“1“
“0“
et4DATA
eVALID
1-2.5 µsec
0.2 µsec
VALID
www.DataShTABLE 2. TIMING DIAGRAM
3
OVERSHOOT
θ2
θ1
SMALL SIGNAL
SETTLING TIME
MAX SLOPE EQUALS
TRACKING RATE (SLEW RATE)
FIGURE 3. STEP RESPONSE INPUT
+
ANGLE
INPUT
e
G
UNITY FEEDBACK
1
DIGITAL
OUTPUT
At 60 Hz
662 ( S + 1)
33
G=
S2 (
S + 1)
330
At 400 Hz
2662 ( S + 1)
133
G=
S2 (
S + 1)
1330
FIGURE 4. S/D CONVERTER LOOP DYNAMICS










Скачать PDF:

[ SDC361.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
SDC36TVS Diode Array for Proximity Switch Input ProtectionSemtech Corporation
Semtech Corporation
SDC361(SDC361 / SDC362) 16-Bit 2 Speed Synchro to Digital and Resolver to Digital ConverterDDC
DDC
SDC362(SDC361 / SDC362) 16-Bit 2 Speed Synchro to Digital and Resolver to Digital ConverterDDC
DDC
SDC36BTVS Diode ArraySemtech
Semtech

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск