|
|
PDF HCD61202U Data sheet ( Hoja de datos )
| Número de pieza | HCD61202U | |
| Descripción | Dot Matrix Liquid Crystal GraphicDisplay Column Driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HCD61202U (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
HD61202U
(Dot Matrix Liquid Crystal GraphicDisplay Column Driver)
Description
HD61202U is a column (segment) driver for dot matrix liquid crystal graphic display systems. It stores
the display data transferred from a 8-bit micro controller in the internal display RAM and generates dot
matrix liquid crystal driving signals.
Each bit data of display RAM corresponds to on/off state of a dot of a liquid crystal display to provide
more flexible than character display.
As it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic
displays with many dots.
www.DataSheet4U.comThe HD61202U, which is produced in the CMOS process, can complete portable battery drive equipment
in combination with a CMOS micro-controller, utilizing the liquid crystal display’s low power
dissipation.
Moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination
with the row (common) driver HD61203U.
Features
• Dot matrix liquid crystal graphic display column driver incorporating display RAM
• RAM data direct display by internal display RAM
RAM bit data 1: On
RAM bit data 0: Off
• Internal display RAM address counter preset, increment
• Display RAM capacity: 512 bytes (4096 bits)
• 8-bit parallel interface
• Internal liquid crystal display driver circuit: 64
• Display duty cycle
Drives liquid crystal panels with 1/32–1/64 duty cycle multiplexing
816
www.DataSheet4U.com
1 page  
www.DataSheet4U.com
HD61202U
HCD61202U PAD Arrangement
No.1
NO.3
NO.27
CHIP CODE
HD61202U
NO.78
NO.54
Chip Size
Coordinate
Origin
Pad Size
: 4.08 × 4.08 mm2
: Pad Center
: Chip center
: 90 × 90 µm2
No.28
No.53
HCD61202U Pad Location Coordinates
PAD PAD Coordinate PAD PAD Coordinate PAD PAD Coordinate
No. Name X
Y
No. Name X
Y
No. Name X Y
PAD PAD Coordinate
No. Name X
Y
1 ADC –1493 1756 26 Y47 –1789 –1508 51 Y22 1452 –1789 76 V3L 1789 1442
2 M –1649 1756 27 Y46 –1789 –1653
3 VCC –1789 1689 28 Y45 –1764 –1789
52 Y21
53 Y20
1604 –1789
1764 –1789
77 V4L 1789 1590
78 GND 1789 1756
4 V4R –1789 1445 29 Y44 –1604 –1789 54 Y19 1789 –1654 79 DB0 1495 1756
5 V3R –1789 1293 30 Y43 –1452 –1789 55 Y18 1789 –1507 80 DB1 1335 1756
6 V2R –1789 1148 31 Y42 –1312 –1789 56 Y17 1789 –1369 81 DB2 1176 1756
7 V1R –1789 1011 32 Y41 –1171 –1789 57 Y16 1789 –1230 82 DB3 1016 1756
8 VEE2 –1789 869 33 Y40 –976 –1789 58 Y15 1789 –1100 83 DB4 854 1756
9 Y64 –1789 721 34 Y39 –846 –1789 59 Y14 1789 –970 84 DB5 694 1756
10 Y63 –1789 591 35 Y38
www.DataSheet4U.com11 Y62 –1789 461 36 Y37
–716 –1789
–586 –1789
60 Y13
61 Y12
1789 –840
1789 –710
85 DB6
86 DB7
535 1756
375 1756
12 Y61 –1789 331 37 Y36 –456 –1789 62 Y11 1789 –580 87 NC
13 Y60 –1789 201 38 Y35 –326 –1789 63 Y10 1789 –450 88 NC
14 Y59 –1789 71 39 Y34 –196 –1789 64 Y9 1789 –320 89 NC
15 Y58 –1789 –60 40 Y33
–65 –1789 65 Y8
1789 –190 90 CS3 218 1756
16 Y57 –1789 –190 41 Y32
65 –1789 66 Y7
1789 –60 91 CS2
62 1756
17 Y56 –1789 –320 42 Y31 195 –1789 67 Y6 1789 71 92 CS1 –94 1756
18 Y55 –1789 –450 43 Y30
325 –1789 68 Y5
1789 201 93 RST –249 1756
19 Y54 –1789 –580 44 Y29
455 –1789 69 Y4
1789 331 94 R/W –405 1756
20 Y53 –1789 –710 45 Y28
585 –1789 70 Y3
1789 461 95 D/I –560 1756
21 Y52 –1789 –840 46 Y27
715 –1789 71 Y2
1789 591 96 CL –716 1756
22 Y51 –1789 –970 47 Y26
845 –1789 72 Y1
1789 721 97 ø2 –871 1756
23 Y50 –1789 –1100 48 Y25
975 –1789 73 VEE1 1789 1024 98 ø1 –1027 1756
24 Y49 –1789 –1230 49 Y24 1170 –1789 74 V1L 1789 1153 99 E –1182 1756
25 Y48 –1789 –1369 50 Y23 1311 –1789 75 V2L 1789 1293 100 FRM –1338 1756
820
www.DataSheet4U.com
5 Page 
www.DataSheet4U.com
HD61202U
Display On/Off Flip/Flop
The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on
state, the display data corresponding to that in RAM is output to the segments. On the other hand, the
display data at all segments disappear in off state independent of the data in RAM. It is controlled by
display on/off instruction. #$% signal = 0 sets the segments in off state. The status of the flip/flop is
output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To
control display data latch by this flip/flop, CL signal (display synchronous signal) should be input
correctly.
Display Start Line Register
The display start line register specifies the line in RAM which corresponds to the top line of LCD panel,
when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen.
6-bit display start line information is written into this register by the display start line set instruction.
When high level of the FRM signal starts the display, the information in this register is transferred to the
Z address counter, which controls the display address, presetting the Z address counter.
X, Y Address Counter
A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3
www.DataSheet4U.combits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions.
1. X address counter
Ordinary register with no count functions. An address is set by instruction.
2. Y address counter
An Address is set by instruction and is increased by 1 automatically by R/W operations of display
data. The Y address counter loops the values of 0 to 63 to count.
Display Data RAM
Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data =
0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can
be reversed by ADC signal.
As the ADC signal controls the Y address counter, reversing of the signal during the operation causes
malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect
ADC pin to VCC or GND when using.
Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and
ADC = 0 (display start line = 0, 1/64 duty cycle).
826
www.DataSheet4U.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HCD61202U.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HCD61202U | Dot Matrix Liquid Crystal GraphicDisplay Column Driver | Hitachi Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |