SCF5250 PDF даташит
Спецификация SCF5250 изготовлена «Motorola Semiconductors» и имеет функцию, называемую «SCF5250 Integrated ColdFire Microprocessor». |
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Детали детали
Номер произв | SCF5250 |
Описание | SCF5250 Integrated ColdFire Microprocessor |
Производители | Motorola Semiconductors |
логотип |
30 Pages
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Freescale Semiconductor
Data Sheet
Document Number: SCF5250EC
Rev. 1.1, 04/2005
SCF5250 Integrated ColdFire®
Microprocessor Data Sheet
1 Introduction
Table of Contents
1 Introduction..........................................................1
This document provides an overview of the SCF5250
www.DataSheet4U.comColdFire® processor and general descriptions of
2 SCF5250 Block Diagram .....................................8
3 Documentation ....................................................8
4 Signal Descriptions..............................................9
SCF5250 features and its various modules.
5 Electrical Characteristics ...................................21
The SCF5250 was designed as a system
6 Pin-Out and Package Information .....................38
controller/decoder for compressed audio music players,
especially portable and automotive CD and hard disk
drive players. The 32-bit ColdFire core with Enhanced
Multiply Accumulate (EMAC) unit provides optimum
performance and code density for the combination of
control code and signal processing required for audio
decoding and post processing, file management, and
system control.
Low power features include a hardwired CD ROM
decoder, advanced 0.13um CMOS process technology,
1.2V core power supply, and on-chip 128KByte SRAM
that enables Windows Media Audio (WMA) decoding
without the need for external DRAM in CD applications.
The SCF5250 is also an excellent general purpose
system controller with over 110 Dhrystone 2.1 MIPS @
120MHz performance at a very competitive price. The
integrated peripherals and enhanced MAC unit allow the
© Freescale Semiconductor, Inc., 2004. All rights reserved.
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Introduction
SCF5250 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can
also be remapped as General Purpose I/O pins.
1.1 Orderable Part Numbers
1.1.1 Orderable Part Table
Orderable Part
Number
SCF5250PV120
SCF5250AG120
SCF5250CPV120
SCF5250CAG120
SCF5250VM120
Table 1. Orderable Part Numbers
Maximum Clock
Frequency
Package Type
Operating
Temperature Range
120 MHz
120 MHz
120 MHz
120 MHz
120 MHz
144 pin QFP
144 pin QFP
144 pin QFP
144 pin QFP
196 ball MAPBGA
-20°C to 70°C
-20°C to 70°C
-40°C to 85°C
-40°C to 85°C
-20°C to 70°C
Part Status
Leaded
Lead Free
Leaded
Lead Free
Lead Free
1.2 SCF5250 Features
1.2.1 ColdFwirewV2wC.oDre ataSheet4U.com
The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to
maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage
pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage
operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then
executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer
that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,
which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline
featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit
(ALU).
1.2.2 DMA Controller
The SCF5250 provides four fully programmable DMA channels for quick data transfer. Single and dual
address mode is supported with the ability to program bursting and cycle stealing. Data transfer is
selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.
Two internal audio channels and the dual UART can be used with the DMA channels. All channels can
perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and
a programmable DMA exception handler.
External requests are not supported.
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
2 Freescale Semiconductor
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Introduction
1.2.3 Enhanced Multiply and Accumulate Module (EMAC)
The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply
instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:
1. Faster signed and unsigned integer multiplies
2. New multiply-accumulate operations supporting signed and unsigned operands
3. New miscellaneous register operations
Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions
for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a
single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution
pipeline.
1.2.4 Instruction Cache
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock. The SCF5250 processor uses a 8K-byte, direct-mapped instruction cache to achieve 107
MIPS at 120 MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an
address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port
sizes to quickly fill cache lines.
1.2.5 Internal 128-KByte SRAM
www.DataSheet4U.comThe 128-KByte on-chip SRAM is available in two banks, SRAM0 (64K) and SRAM1 (64K). It provides
one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or
data segments to maximize performance. Memory in SRAM1 can be accessed under DMA.
1.2.6 SDRAM Controller
The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM up to 32 MB (256
Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in
system memory size without rerouting address lines and rewiring boards. The controller operates in page
mode, non-page mode, and burst-page mode and supports SDRAMS.
1.2.7 System Interface
The SCF5250 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with
independent programmable control of the assertion and negation of chip-select and write-enable signals.
The SCF5250 also supports bursting ROMs.
1.2.8 External Bus Interface
The bus interface controller transfers information between the ColdFire core or DMA and memory,
peripherals, or other devices on the external bus. The external bus interface provides 23 bits of address bus
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
3
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