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W78E62B PDF даташит

Спецификация W78E62B изготовлена ​​​​«Winbond» и имеет функцию, называемую «8-Bit Microcontroller».

Детали детали

Номер произв W78E62B
Описание 8-Bit Microcontroller
Производители Winbond
логотип Winbond логотип 

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W78E62B Даташит, Описание, Даташиты
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W78E62B
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78E62B is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78E62B is fully compatible with the standard 8052.
The W78E62B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which
allows the contents of the 64KB main MTP-ROM to be updated by the loader program located at the
4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O
ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are
supported by a eight sources two-level interrupt capability. To facilitate programming and verification,
the MTP-ROM inside the W78E62B allows the program memory to be programmed and read
electronically. Once the code is confirmed, the user can protect the code for security.
The W78E62B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller up to 40 MHz.
www.DataSheet4U.com64K bytes of in-system programmable MTP-ROM for Application Program (APROM).
4K bytes of auxiliary MTP-ROM for Loader Program (LDROM).
Low standby current at full supply voltage.
512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
64K bytes program memory address space and 64K bytes data memory address space.
Four 8-bit bi-directional ports.
One 4-bit multipurpose programmable port.
Build-in 74373 and 74244 logical functions on Port 2.(software programmable)
Three 16-bit timer/counters
One full duplex serial port
Eight-sources, two-level interrupt capability
Built-in power management
Code protection
PACKAGE
PLCC 44: W78E62BP-40
LQFP 48: W78E62BD-40
Publication Release Date: June 1999
- 1 - Revision A1
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W78E62B Даташит, Описание, Даташиты
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W78E62B
PIN CONFIGURATIONS
48-Pin LQFP (W78E62BD)
/
TI
2 N AA A A
E TT
DD D D
X 23
01 2 3
N
P
.
PP P
.
P
.
P
.. . .
PP P P
.
C
.
1 11 1
. .. .
4 32 1
1
.
0
4
.
2
V
D
D
0
.
0
0
.
1
00
..
23
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2,P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
N.C.
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
N.C.
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P P X X VP P P P P P N
3 3 T T S4 2 2 2 2 2 .
. . A A S. . . . . . C
67 L L
0 01 2 3 4 .
, , 21
,, , , ,
//
AA A A A
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44-Pin PLCC (W78E62BP)
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2,P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
/
TI
2 N AA A A
E TT
DD D D
X 23
01 2 3
. ..
.. . .
PP P P PPV PP P P
11 1 1 14D 00 0 0
. . . . . . D. . . .
43 2 1 02
01 2 3
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P P X X VP P P P P P
3 3 T T S4 2 2 2 2 2
. . A A S. . . . . .
67 L L
0 01 2 3 4
, , 21
,, , , ,
//
AA A A A
WR
89 1 1 1
RD
012
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-2-
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W78E62B Даташит, Описание, Даташиты
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W78E62B
PIN DESCRIPTION
SYMBOL
EA
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0P0.7
P1.0P1.7
P2.0P2.7
P3.0P3.7
P4.0P4.3
TYPE
DESCRIPTIONS
I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high and the program counter is within the 64 KB area.
OH
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
OH
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.
I L RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
www.DataSheet4U.comI GROUND: ground potential.
I POWER SUPPLY: Supply voltage for operation.
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. It also can
be programmed to be an output-latched port like an on-chip 74373, or a
buffer input port like an on-chip 74244.
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O port with alternate function. See details below.
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Port 4
Port 4, SFR P4 at address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be
configured individually by software. The Port 4 has four different operation mode:
In mode 0, P4.0P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt INT3 and INT2 if enabled.
In mode 1, P4.0P4.3 are read data strobe signals which are synchronized with RD signal at
specified addresses. These signals can be used as chip-select signals for external peripherals.
Publication Release Date: June 1999
- 3 - Revision A1
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