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PDF HD6417604 Data sheet ( Hoja de datos )
| Número de pieza | HD6417604 | |
| Descripción | Microcontroller | |
| Fabricantes | Renesas | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
DataSheet4U.com
Renesas Technology Corp. DataShee
Customer Support Dept.
April 1, 2003
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Preface
The SH7604 implements high-performance operations by using a CPU which employs the
Reduced Instruction Set Computer (RISC) system. The SH7604 is a new-generation RISC
microcomputer which realizes low power consumption, an essential feature of microcomputer
devices, as well as integrating peripheral features necessary for system configuration.
The CPU of the SH7604 has a set of RISC-type instructions; basic instructions operate at one state
per instruction, that is, in one system clock cycle, dramatically increasing execution speeds. The
SH7604 incorporates a 32-bit multiplier which performs high-speed sum-of-product (multiply-
and-accumulate) operations. Instructions used by the SH7604 are upwardly compatible with the
SH7000 Series, allowing easy migration from the SH7000 Series to the SH7604.
Moreover, the SH7604 incorporates on-chip peripheral modules such as an interrupt controller
(INTC), direct memory access controller (DMAC), division unit (DIVU), timers (FRT, WDT),
and serial communication interface (SCI), so that a user system can be configured using the
minimum number of parts.
On-chip cache memory enhances the CPU throughput. A bus control feature, which supports
external memory access, improves external memory access efficiency, allowing direct connection
to synchronous DRAM, DRAM, and pseudo-SRAM without the help of glue logic.
This hardware manual explains the harDdwaatareSfheeaetutr4eUs .ocfotmhe SH7604. For details of instructions,
see the Programming Manual.
Related Documents
et4U.com
SH7604 instructions
“SH-1/SH-2 Programming Manual” (Document No.: ADE-602-063B)
For the development environment system, call your nearest Hitachi sales office.
DataShee
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5.2.3 IRL Interrupts ....................................................................................................... 83
5.2.4 On-chip Peripheral Module Interrupts.................................................................. 85
5.2.5 Interrupt Exception Vectors and Priority Order ................................................... 86
5.3 Description of Registers .................................................................................................... 88
5.3.1 Interrupt Priority Level Setting Register A (IPRA) ............................................. 88
5.3.2 Interrupt Priority Level Setting Register B (IPRB).............................................. 89
5.3.3 Vector Number Setting Register WDT (VCRWDT) ........................................... 91
5.3.4 Vector Number Setting Register A (VCRA)........................................................ 91
5.3.5 Vector Number Setting Register B (VCRB) ........................................................ 92
5.3.6 Vector Number Setting Register C (VCRC) ........................................................ 93
5.3.7 Vector Number Setting Register D (VCRD)........................................................ 94
5.3.8 Interrupt Control Register (ICR) .......................................................................... 95
5.4 Interrupt Operation ............................................................................................................ 97
5.4.1 Interrupt Sequence................................................................................................ 97
5.4.2 Stack after Interrupt Exception Handling............................................................. 99
5.5 Interrupt Response Time.................................................................................................... 100
5.6 Sampling of Pins IRL3–IRL0............................................................................................ 101
5.7 Usage Notes ....................................................................................................................... 103
Section 6 User Break Controller ................................................................................... 107
6.1 Overview............................................................................................................................ 107
6.1.1 Features ................................................................................................................ 107
6.1.2 Block Diagram..............D...a..t.a...S..h..e...e..t.4..U....c..o...m.......................................................... 108
6.1.3 Register Configuration ......................................................................................... 109
6.2 Register Descriptions......................................................................................................... 110
6.2.1 Break Address Register A (BARA) ..................................................................... 110
et4U.com 6.2.2 Break Address Mask Register A (BAMRA)........................................................ 1D1a1taShee
6.2.3 Break Bus Cycle Register A (BBRA) .................................................................. 112
6.2.4 Break Address Register B (BARB)...................................................................... 114
6.2.5 Break Address Mask Register B (BAMRB) ........................................................ 114
6.2.6 Break Data Register B (BDRB) ........................................................................... 114
6.2.7 Break Data Mask Register B (BDMRB).............................................................. 115
6.2.8 Bus Break Register B (BBRB) ............................................................................. 116
6.2.9 Break Control Register (BRCR) .......................................................................... 116
6.3 Operation ........................................................................................................................... 120
6.3.1 Flow of the User Break Operation........................................................................ 120
6.3.2 Break on Instruction Fetch Cycle ......................................................................... 120
6.3.3 Break on Data Access Cycle ................................................................................ 121
6.3.4 Break on External Bus Cycle ............................................................................... 122
6.3.5 Program Counter (PC) Values Saved ................................................................... 122
DataSheet4U6..c3o.6m Example of Use .................................................................................................... 123
6.3.7 Usage Notes.......................................................................................................... 126
6.3.8 SH7000 Series Compatible Mode ........................................................................ 127
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| PDF Descargar | [ Datasheet HD6417604.PDF ] | |
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